e1000g_sw.h revision 6ad5fc39c6f3b123ae5588d60fc8dfe068e07bfc
1N/A * This file is provided under a CDDLv1 license. When using or 1N/A * redistributing this file, you may do so under this license. 1N/A * In redistributing this file this license must be included 1N/A * and no other modification of this header file is permitted. 1N/A * CDDL LICENSE SUMMARY 1N/A * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 1N/A * The contents of this file are subject to the terms of Version 1N/A * 1.0 of the Common Development and Distribution License (the "License"). 1N/A * You should have received a copy of the License with this software. 1N/A * You can obtain a copy of the License at 1N/A * See the License for the specific language governing permissions 1N/A * and limitations under the License. 1N/A * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 1N/A * Use is subject to license terms of the CDDLv1. 1N/A#
pragma ident "%Z%%M% %I% %E% SMI" 1N/A * ********************************************************************** 1N/A * This header file contains Software-related data structures * 1N/A * ********************************************************************** * constants used in setting flow control thresholds /* which is normally 0x040 */ * definitions for smartspeed workaround * Definitions for module_info. #
define WSNAME "e1000g" /* module name */ * Defined for IP header alignment. We also need to preserve space for * bit flags for 'attach_progress' which is a member variable in struct e1000g * Speed and Duplex Settings * Coexist Workaround RP: 07/04/03 * 82544 Workaround : Co-existence * Defines for Jumbo Frame /* The sizes (in bytes) of a ethernet packet */ /* Defines for Tx stall check */ * Private dip list definitions * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does * not remove the head from the queue. * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), * and return it (this differs from QUEUE_REMOVE_HEAD only in * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not * remove the tail from the queue. * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. * QUEUE_GET_NEXT -- Macro which returns the next element linked to the * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue * Shorthand for the NDD parameters * E1000G-specific ioctls ... #
define E1000G_IOC (((((((
'E' <<
4) +
'1') <<
4) \
+
'K') <<
4) +
'G') <<
4)
* These diagnostic IOCTLS are enabled only in DEBUG drivers #
endif /* E1000G_DEBUG */ * (Internal) return values from ioctl subroutines * Named Data (ND) Parameter Management Structure * NDD parameter indexes, divided into: * read-only parameters describing the hardware's capabilities * read-write parameters controlling the advertised capabilities * read-only parameters describing the partner's capabilities * read-write parameters controlling the force speed and duplex * read-only parameters describing the link state * read-only parameters describing the driver properties * read-write parameters controlling the driver properties * The entry of the private dip list * A structure that points to the next entry in the queue. * A "ListHead" structure that points to the head and tail of a queue * Address-Length pair structure that stores descriptor info * Transmit Control Block (TCB), Ndis equiv of SWPacket This * structure stores the additional information that is * associated with every packet to be transmitted. It stores the * message block pointer and the TBD addresses associated with * the m_blk and also the link to the next tcb in the chain /* Link to the next tx_sw_packet in the list */ * This structure is similar to the rx_sw_packet structure used * for Ndis. This structure stores information about the 2k * aligned receive buffer into which the FX1000 DMA's frames. * This structure is maintained as a linked list of many * receiver buffer pointers. /* Link to the next rx_sw_packet_t in the list */ * Descriptor queue definitions * Software packet structures definitions * Timer definitions for 82547 * reschedule when tx resource is available * Descriptor queue definitions * Software packet structures definitions * Rx and Tx packet count for interrupt adaptive setting * The watchdog_lock must be held when updateing the * timeout fields in struct e1000g, that is, * watchdog_tid, watchdog_timer_started. * The link_lock protects the link fields in struct e1000g, * such as link_state, link_speed, link_duplex, link_complete, and * The chip_lock assures that the Rx/Tx process must be * stopped while other functions change the hardware * configuration of e1000g card, such as e1000g_reset(), * e1000g_reset_hw() etc are executed. #
endif /* _E1000G_SW_H */