e1000_defines.h revision bd9f6899328e19cbb74e3ad02f5c32002285887e
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * This file is provided under a CDDLv1 license. When using or
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * redistributing this file, you may do so under this license.
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin * In redistributing this file this license must be included
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * and no other modification of this header file is permitted.
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin * CDDL LICENSE SUMMARY
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * The contents of this file are subject to the terms of Version
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * 1.0 of the Common Development and Distribution License (the "License").
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * You should have received a copy of the License with this software.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * You can obtain a copy of the License at
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * See the License for the specific language governing permissions
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * and limitations under the License.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Use is subject to license terms of the CDDLv1.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * IntelVersion: 1.118 v3-1-10-1_2009-9-18_Release14-6
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Definitions for power management and wakeup registers */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Wake Up Control */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Wake Up Filter Control */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Mask for all wakeup filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Mask for 4 flexible filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Mask for 6 wakeup filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Mask for 6 flexible filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Mask for all 6 wakeup filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Offset to the Flexible Filters bits */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Mask for the 4 flexible filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Mask for 6 flexible filters */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Wake Up Status */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Wake Up Packet Length */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Four Flexible Filters are supported */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Six Flexible Filters are supported */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Each Flexible Filter is at most 128 (0x80) bytes in length */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Extended Device Control */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Reserved (bits 4,5) in >= 82575 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* DMA Dynamic Clock Gating */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* IAME enable bit (27) was removed in >= 82575 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_IAME 0x08000000 /* Int acknowledge Auto-mask */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* packet buffer parity error detection enabled */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* descriptor FIFO parity error detection enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Receive Descriptor bit definitions */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* mask to determine if packets should be dropped due to frame errors */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Same mask, but for extended and packet split descriptors */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Management Control */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Enable Neighbor Discovery Filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Enable MAC address filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Enable MNG packets to host memory */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Enable IP address filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable cksum filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Receive Control */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min thresh size */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min thresh size */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min thresh size */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Use byte values for the following shift parameters
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * E1000_PSRCTL_BSIZE0_MASK) |
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * E1000_PSRCTL_BSIZE1_MASK) |
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * E1000_PSRCTL_BSIZE2_MASK) |
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * E1000_PSRCTL_BSIZE3_MASK))
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * where value0 = [128..16256], default=256
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * value1 = [1024..64512], default=4096
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * value2 = [0..64512], default=4096
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * value3 = [0..64512], default=0
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* SWFW_SYNC Definitions */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* FACTPS Definitions */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Device Control */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /* Block new Master reqs */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Defined polarity of Dock/Undock indication in SDP[0] */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Reset both PHY ports, through PHYRST_N pin */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* enable link status from external LINK_0 and LINK_1 pins */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* Initiate an interrupt to ME */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Bit definitions for the Management Data IO (MDIO) and Management Data
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Clock (MDC) pins in the Device Control Register.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
#define E1000_PCS_LSTS_SPEED_10 0
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
#define POLL_IMS_ENABLE_MASK ( \
E1000_IMS_RXDMT0 | \
#define IMS_ENABLE_MASK ( \
E1000_IMS_RXT0 | \
E1000_IMS_TXDW | \
E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ | \
#define E1000_SUCCESS 0
#ifndef E1000_NVM_GRANT_ATTEMPTS
#define NVM_MAC_ADDR_OFFSET 0
#ifndef ETH_ADDR_LEN
#define GG82563_PHY_SPEC_CTRL \
#define GG82563_PHY_SPEC_STATUS \
#define GG82563_PHY_INT_ENABLE \
#define GG82563_PHY_SPEC_STATUS_2 \
#define GG82563_PHY_RX_ERR_CNTR \
#define GG82563_PHY_PAGE_SELECT \
#define GG82563_PHY_SPEC_CTRL_2 \
#define GG82563_PHY_PAGE_SELECT_ALT \
#define GG82563_PHY_TEST_CLK_CTRL \
#define GG82563_PHY_MAC_SPEC_CTRL \
#define GG82563_PHY_MAC_SPEC_CTRL_2 \
#define GG82563_PHY_DSP_DISTANCE \
#define GG82563_PHY_KMRN_MODE_CTRL \
#define GG82563_PHY_PORT_RESET \
#define GG82563_PHY_REVISION_ID \
#define GG82563_PHY_DEVICE_ID \
#define GG82563_PHY_PWR_MGMT_CTRL \
#define GG82563_PHY_RATE_ADAPT_CTRL \
#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
#define GG82563_PHY_KMRN_CTRL \
#define GG82563_PHY_INBAND_CTRL \
#define GG82563_PHY_KMRN_DIAGNOSTIC \
#define GG82563_PHY_ACK_TIMEOUTS \
#define GG82563_PHY_ADV_ABILITY \
#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
#define GG82563_PHY_ADV_NEXT_PAGE \
#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
#define GG82563_PHY_KMRN_MISC \