e1000_80003es2lan.c revision bd9f6899328e19cbb74e3ad02f5c32002285887e
/*
* This file is provided under a CDDLv1 license. When using or
* redistributing this file, you may do so under this license.
* In redistributing this file this license must be included
* and no other modification of this header file is permitted.
*
* CDDL LICENSE SUMMARY
*
* Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
*
* The contents of this file are subject to the terms of Version
* 1.0 of the Common Development and Distribution License (the "License").
*
* You should have received a copy of the License with this software.
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDLv1.
*/
/*
* IntelVersion: 1.86 v3-1-10-1_2009-9-18_Release14-6
*/
/*
* 80003ES2LAN Gigabit Ethernet Controller (Copper)
* 80003ES2LAN Gigabit Ethernet Controller (Serdes)
*/
#include "e1000_api.h"
/*
* A table for the GG82563 cable length where the range is defined with a
* lower bound at "index" and the upper bound at "index + 5".
*/
static const u16 e1000_gg82563_cable_length_table[] =
{0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF};
#define GG82563_CABLE_LENGTH_TABLE_SIZE \
(sizeof (e1000_gg82563_cable_length_table) / \
sizeof (e1000_gg82563_cable_length_table[0]))
/*
* e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_phy_params_80003es2lan");
goto out;
} else {
}
/* This can only be done after all function pointers are setup. */
/* Verify phy id */
ret_val = -E1000_ERR_PHY;
goto out;
}
out:
return (ret_val);
}
/*
* e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
break;
break;
default:
break;
}
/*
* Added to a constant, "size" becomes the left-shift value
* for setting word_size.
*/
/* EEPROM access above 16k is unsupported */
if (size > 14)
size = 14;
/* Function Pointers */
return (E1000_SUCCESS);
}
/*
* e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_mac_params_80003es2lan");
/* Set media type */
break;
default:
break;
}
/* Set mta register count */
/* Set rar entry count */
/* Set if part includes ASF firmware */
mac->asf_firmware_present = true;
/* Set if manageability features are enabled. */
? true : false;
/* Function pointers */
/* reset */
/* hw initialization */
/* link setup */
/* physical interface link setup */
/* check for link */
case e1000_media_type_copper:
break;
case e1000_media_type_fiber:
break;
break;
default:
goto out;
}
/* check management mode */
/* multicast address update */
/* writing VFTA */
/* clearing VFTA */
/* setting MTA */
/* read mac address */
/* ID LED init */
/* blink LED */
/* setup LED */
/* cleanup LED */
/* clear hardware counters */
/* link info */
/* set lan id for port to determine which phy lock to use */
out:
return (ret_val);
}
/*
* e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
* @hw: pointer to the HW structure
*
* Called to initialize all function pointers and parameters.
*/
void
{
DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
}
/*
* e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
* @hw: pointer to the HW structure
*
* A wrapper to acquire access rights to the correct PHY.
*/
static s32
{
DEBUGFUNC("e1000_acquire_phy_80003es2lan");
}
/*
* e1000_release_phy_80003es2lan - Release rights to access PHY
* @hw: pointer to the HW structure
*
* A wrapper to release access rights to the correct PHY.
*/
static void
{
DEBUGFUNC("e1000_release_phy_80003es2lan");
}
/*
* e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
* @hw: pointer to the HW structure
*
* Acquire the semaphore to access the Kumeran interface.
*
*/
static s32
{
DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
}
/*
* e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
* @hw: pointer to the HW structure
*
* Release the semaphore used to access the Kumeran interface
*/
static void
{
DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
}
/*
* e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
* @hw: pointer to the HW structure
*
* Acquire the semaphore to access the EEPROM.
*/
static s32
{
DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
if (ret_val)
goto out;
if (ret_val)
out:
return (ret_val);
}
/*
* e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
* @hw: pointer to the HW structure
*
* Release the semaphore used to access the EEPROM.
*/
static void
{
DEBUGFUNC("e1000_release_nvm_80003es2lan");
}
/*
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* will also specify which port we're acquiring the lock for.
*/
static s32
{
DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
while (i < timeout) {
if (e1000_get_hw_semaphore_generic(hw)) {
goto out;
}
break;
/*
* Firmware currently using resource (fwmask)
* or other software thread using resource (swmask)
*/
msec_delay_irq(5);
i++;
}
if (i == timeout) {
DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
goto out;
}
out:
return (ret_val);
}
/*
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* will also specify which port we're releasing the lock for.
*/
static void
{
DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
/* Empty */
}
}
/*
* e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
* @hw: pointer to the HW structure
* @offset: offset of the register to read
* @data: pointer to the data returned from the operation
*
* Read the GG82563 PHY register.
*/
static s32
{
DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
if (ret_val)
goto out;
/* Select Configuration Page */
} else {
/*
* Use Alternative Page Select register to access
* registers 30 and 31
*/
}
if (ret_val) {
goto out;
}
/*
* The "ready" bit in the MDIC register may be incorrectly set
* before the device has completed the "Page Select" MDI
* transaction. So we wait 200us after each MDI command...
*/
usec_delay(200);
/* ...and verify the command was successful. */
ret_val = -E1000_ERR_PHY;
goto out;
}
usec_delay(200);
data);
usec_delay(200);
} else
data);
out:
return (ret_val);
}
/*
* e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
* @hw: pointer to the HW structure
* @offset: offset of the register to read
* @data: value to write to the register
*
* Write to the GG82563 PHY register.
*/
static s32
{
DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
if (ret_val)
goto out;
/* Select Configuration Page */
} else {
/*
* Use Alternative Page Select register to access
* registers 30 and 31
*/
}
if (ret_val) {
goto out;
}
/*
* The "ready" bit in the MDIC register may be incorrectly set
* before the device has completed the "Page Select" MDI
* transaction. So we wait 200us after each MDI command...
*/
usec_delay(200);
/* ...and verify the command was successful. */
ret_val = -E1000_ERR_PHY;
goto out;
}
usec_delay(200);
data);
usec_delay(200);
} else
data);
out:
return (ret_val);
}
/*
* e1000_write_nvm_80003es2lan - Write to ESB2 NVM
* @hw: pointer to the HW structure
* @offset: offset of the register to read
* @words: number of words to write
* @data: buffer of data to write to the NVM
*
* Write "words" of data to the ESB2 NVM.
*/
static s32
{
DEBUGFUNC("e1000_write_nvm_80003es2lan");
}
/*
* e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
* @hw: pointer to the HW structure
*
* Wait a specific amount of time for manageability processes to complete.
* This is a function pointer entry point called by the phy module.
*/
static s32
{
DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
while (timeout) {
break;
msec_delay(1);
timeout--;
}
if (!timeout) {
DEBUGOUT("MNG configuration cycle has not completed.\n");
goto out;
}
out:
return (ret_val);
}
/*
* e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
* @hw: pointer to the HW structure
*
* Force the speed and duplex settings onto the PHY. This is a
* function pointer entry point called by the phy module.
*/
static s32
{
bool link;
DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
goto out;
/*
* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
* forced whenever speed and duplex are forced.
*/
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
/* Reset the phy to commit changes. */
phy_data |= MII_CR_RESET;
if (ret_val)
goto out;
usec_delay(1);
"on GG82563 phy.\n");
100000, &link);
if (ret_val)
goto out;
if (!link) {
/*
* We didn't get link.
* Reset the DSP and cross our fingers.
*/
if (ret_val)
goto out;
}
/* Try once more */
100000, &link);
if (ret_val)
goto out;
}
ret_val =
if (ret_val)
goto out;
/*
* Resetting the phy means we need to verify the TX_CLK corresponds
* to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
*/
else
/*
* In addition, we must re-enable CRS on Tx for both half and full
* duplex.
*/
ret_val =
out:
return (ret_val);
}
/*
* e1000_get_cable_length_80003es2lan - Set approximate cable length
* @hw: pointer to the HW structure
*
* Find the approximate cable length as measured by the GG82563 PHY.
* This is a function pointer entry point called by the phy module.
*/
static s32
{
DEBUGFUNC("e1000_get_cable_length_80003es2lan");
goto out;
if (ret_val)
goto out;
goto out;
}
out:
return (ret_val);
}
/*
* e1000_get_link_up_info_80003es2lan - Report speed and duplex
* @hw: pointer to the HW structure
* @speed: pointer to speed buffer
* @duplex: pointer to duplex buffer
*
* Retrieve the current speed and duplex configuration.
*/
static s32
{
DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
duplex);
} else {
duplex);
}
return (ret_val);
}
/*
* e1000_reset_hw_80003es2lan - Reset the ESB2 controller
* @hw: pointer to the HW structure
*
* Perform a global reset to the ESB2 controller.
*/
static s32
{
DEBUGFUNC("e1000_reset_hw_80003es2lan");
/*
* Prevent the PCI-E bus from sticking if there is no TLP connection
*/
if (ret_val)
DEBUGOUT("PCI-E Master disable polling has failed.\n");
DEBUGOUT("Masking off all interrupts\n");
msec_delay(10);
DEBUGOUT("Issuing a global reset to MAC\n");
if (ret_val)
/* We don't want to continue accessing MAC registers. */
goto out;
/* Clear any pending interrupt events. */
out:
return (ret_val);
}
/*
* e1000_init_hw_80003es2lan - Initialize the ESB2 controller
* @hw: pointer to the HW structure
*
* Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
*/
static s32
{
u16 i;
DEBUGFUNC("e1000_init_hw_80003es2lan");
/* Initialize identification LED */
if (ret_val) {
DEBUGOUT("Error initializing identification LED\n");
/* This is not fatal and we should not stop init due to this */
}
/* Disabling VLAN filtering */
DEBUGOUT("Initializing the IEEE VLAN\n");
/* Setup the receive address. */
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
/* Setup link and flow control */
/* Set the transmit descriptor write-back policy */
/* ...for both queues. */
/* Enable retransmit on late collisions */
/* Configure Gigabit Carry Extend Padding */
/* Configure Transmit Inter-Packet Gap */
reg_data &= ~0x00100000;
/* default to true to enable the MDIC W/A */
&i);
if (!ret_val) {
if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
}
/*
* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
*/
return (ret_val);
}
/*
* e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
* @hw: pointer to the HW structure
*
* Initializes required hardware-dependent bits needed for normal operation.
*/
static void
{
DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
/* Transmit Descriptor Control 0 */
/* Transmit Descriptor Control 1 */
/* Transmit Arbitration Control 0 */
/* Transmit Arbitration Control 1 */
else
}
/*
* e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
* @hw: pointer to the HW structure
*
* Setup some GG82563 PHY registers for obtaining link
*/
static s32
{
DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
if (!phy->reset_disable) {
&data);
if (ret_val)
goto out;
/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
data);
if (ret_val)
goto out;
/*
* Options:
* 0 - Auto for all speeds
* 1 - MDI mode
* 2 - MDI-X mode
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
*/
ret_val =
if (ret_val)
goto out;
case 1:
break;
case 2:
break;
case 0:
default:
break;
}
/*
* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* 1 - Enabled
*/
ret_val =
if (ret_val)
goto out;
/* SW Reset the PHY so all changes take effect */
if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
goto out;
}
}
/* Bypass Rx and Tx FIFO's */
if (ret_val)
goto out;
&data);
if (ret_val)
goto out;
data);
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
/*
* Do not init these registers when the HW is in IAMT mode, since the
* firmware will have already initialized them. We only initialize
* them if the HW is not in IAMT mode.
*/
/* Enable Electrical Idle on the PHY */
data);
if (ret_val)
goto out;
&data);
if (ret_val)
goto out;
data);
if (ret_val)
goto out;
}
/*
* Workaround: Disable padding in Kumeran interface in the MAC
* and in the PHY to avoid CRC errors.
*/
if (ret_val)
goto out;
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
* @hw: pointer to the HW structure
*
* Essentially a wrapper for setting up all things "copper" related.
* This is a function pointer entry point called by the mac module.
*/
static s32
{
DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
ctrl |= E1000_CTRL_SLU;
/*
* Set the mac to wait the maximum time between each
* iteration and increase the max iterations when
* polling the phy; this fixes erroneous timeouts at 10Mbps.
*/
0xFFFF);
if (ret_val)
goto out;
®_data);
if (ret_val)
goto out;
reg_data |= 0x3F;
reg_data);
if (ret_val)
goto out;
®_data);
if (ret_val)
goto out;
reg_data);
if (ret_val)
goto out;
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
* @hw: pointer to the HW structure
* @duplex: current duplex setting
*
* Configure the KMRN interface by applying last minute quirks for
* 10/100 operation.
*/
static s32
{
DEBUGFUNC("e1000_configure_on_link_up");
&speed,
&duplex);
if (ret_val)
goto out;
if (speed == SPEED_1000)
else
}
out:
return (ret_val);
}
/*
* e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
* @hw: pointer to the HW structure
* @duplex: current duplex setting
*
* Configure the KMRN interface by applying last minute quirks for
* 10/100 operation.
*/
static s32
{
u32 i = 0;
DEBUGFUNC("e1000_configure_kmrn_for_10_100");
reg_data);
if (ret_val)
goto out;
/* Configure Transmit Inter-Packet Gap */
tipg &= ~E1000_TIPG_IPGT_MASK;
do {
®_data);
if (ret_val)
goto out;
®_data2);
if (ret_val)
goto out;
i++;
if (duplex == HALF_DUPLEX)
else
ret_val =
out:
return (ret_val);
}
/*
* e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
* @hw: pointer to the HW structure
*
* Configure the KMRN interface by applying last minute quirks for
* gigabit operation.
*/
static s32
{
u32 i = 0;
DEBUGFUNC("e1000_configure_kmrn_for_1000");
reg_data);
if (ret_val)
goto out;
/* Configure Transmit Inter-Packet Gap */
tipg &= ~E1000_TIPG_IPGT_MASK;
do {
®_data);
if (ret_val)
goto out;
®_data2);
if (ret_val)
goto out;
i++;
ret_val =
out:
return (ret_val);
}
/*
* e1000_read_kmrn_reg_80003es2lan - Read kumeran register
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* Acquire semaphore, then read the PHY register at offset
* using the kumeran interface. The information retrieved is stored in data.
* Release the semaphore before exiting.
*/
static s32
{
DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
if (ret_val)
goto out;
usec_delay(2);
out:
return (ret_val);
}
/*
* e1000_write_kmrn_reg_80003es2lan - Write kumeran register
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write at register offset
*
* Acquire semaphore, then write the data to PHY register
* at the offset using the kumeran interface. Release semaphore
* before exiting.
*/
static s32
{
DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
if (ret_val)
goto out;
usec_delay(2);
out:
return (ret_val);
}
/*
* e1000_read_mac_addr_80003es2lan - Read device MAC address
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
/*
* If there's an alternate MAC address place it in RAR0
* so that it will override the Si installed default perm
* address.
*/
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
* @hw: pointer to the HW structure
*
* In the case of a PHY power down to save power, or to turn off link during a
* driver unload, or wake on lan is not enabled, remove the link.
*/
static void
{
/* If the management interface is not enabled, then power down */
}
/*
* e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
* @hw: pointer to the HW structure
*
* Clears the hardware counters by reading the counter registers.
*/
static void
{
DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
}