e1000_vf.h revision 75eba5b6d79ed4d2ce3daf7b2806306b6b69a938
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/******************************************************************************
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi Copyright (c) 2001-2010, Intel Corporation
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi All rights reserved.
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi modification, are permitted provided that the following conditions are met:
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi this list of conditions and the following disclaimer.
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi******************************************************************************/
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Additional Descriptor Control definitions */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* SRRCTL bit definitions */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Interrupt Defines */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EITR(_n) (0x01680 + ((_n) << 2))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Receive Descriptor - Advanced */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* RSS type, Packet type */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Split Header, header buffer len */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Transmit Descriptor - Advanced */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi u64 buffer_addr; /* Address of descriptor's data buf */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Adv Transmit Descriptor Config Masks */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Context descriptors */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi /* Function pointers for the MAC. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi void (*write_vfta)(struct e1000_hw *, u32, u32);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi void (*rar_set)(struct e1000_hw *, u8*, u32);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*check_for_msg)(struct e1000_hw *, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*check_for_ack)(struct e1000_hw *, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi s32 (*check_for_rst)(struct e1000_hw *, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi unsigned long io_base;
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_promisc_disabled = 0, /* all promisc modes disabled */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_promisc_unicast = 1, /* unicast promiscuous enabled */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_promisc_multicast = 2, /* multicast promiscuous enabled */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi e1000_promisc_enabled = 3, /* both uni and multicast promisc */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* These functions must be implemented by drivers */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_rlpml_set_vf(struct e1000_hw *, u16);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#endif /* _E1000_VF_H_ */