75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/******************************************************************************
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi Copyright (c) 2001-2015, Intel Corporation
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi All rights reserved.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi Redistribution and use in source and binary forms, with or without
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi modification, are permitted provided that the following conditions are met:
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 1. Redistributions of source code must retain the above copyright notice,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi this list of conditions and the following disclaimer.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 2. Redistributions in binary form must reproduce the above copyright
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi notice, this list of conditions and the following disclaimer in the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi documentation and/or other materials provided with the distribution.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi contributors may be used to endorse or promote products derived from
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi this software without specific prior written permission.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi POSSIBILITY OF SUCH DAMAGE.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi******************************************************************************/
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Requires up to 10 seconds when MNG might be accessing part. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* FW established a valid mode */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Shared Receive Address Registers */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi/* FEXT register bit definition */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi/* bit for disabling packet buffer read */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field*/
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* PHY Wakeup Registers and defines */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi/* Half-duplex collision counts */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* SMBus Control Phy Register */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi/* I218 Ultra Low Power Configuration 1 Register */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi/* enable ULP even if when phy powered down via lanphypc */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi/* disable clear of sticky ULP on PERST */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* SMBus Address Phy Register */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Strapping Option Register - RO */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_STRAP_SMT_FREQ_MASK 0x00003000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* OEM Bits Phy Register */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* KMRN Mode Control */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* KMRN FIFO Control and Status */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* PHY Power Management Control */
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi/* Inband Control */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi/* Low Power Idle GPIO Control */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* PHY Low Power Idle Control */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi/* 82579 DFT Control */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Extended Management Interface (EMI) Registers */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82579_RX_CONFIG 0x3412 /* Receive configuration */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define I217_RX_CONFIG 0xB20C /* Receive configuration */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Intel Rapid Start Technology Support */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Receive Address Initial CRC Calculation */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Latency Tolerance Reporting */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Proprietary Latency Tolerance Reporting PCI Capability */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* OBFF Control & Threshold Defines */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchiu32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchivoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchis32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_set_eee_pchlan(struct e1000_hw *hw);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchis32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#endif /* _E1000_ICH8LAN_H_ */