75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/******************************************************************************
49b7860084dbba18bc00b29413d6182197f9fe93Robert Mustacchi Copyright (c) 2001-2015, Intel Corporation
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi All rights reserved.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi Redistribution and use in source and binary forms, with or without
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi modification, are permitted provided that the following conditions are met:
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 1. Redistributions of source code must retain the above copyright notice,
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi this list of conditions and the following disclaimer.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 2. Redistributions in binary form must reproduce the above copyright
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi notice, this list of conditions and the following disclaimer in the
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi documentation and/or other materials provided with the distribution.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi this software without specific prior written permission.
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi******************************************************************************/
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* PHY Specific Control Register 2 (Page 0, Register 26) */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* MAC Specific Control Register (Page 2, Register 21) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
c124a83e09115de88ecccd4f689983f42a1d53bdRobert Mustacchi/* DSP Distance Register (Page 5, Register 26)
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 2 = 80-100M
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi * 3 = 110-140M
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Kumeran Mode Control Register (Page 193, Register 16) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Max number of times Kumeran read/write should be validated */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* Power Management Control Register (Page 193, Register 20) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* 1=Enable SERDES Electrical Idle */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi/* In-Band Control Register (Page 194, Register 18) */
75eba5b6d79ed4d2ce3daf7b2806306b6b69a938Robert Mustacchi#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */