t4_msg.h revision 56b2bdd1f04d465cfe4a95b88ae5cba5884154e4
/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
*/
/*
* Definitions of T4 work request and CPL5 commands and status codes.
*
* Copyright (C) 2008-2013 Chelsio Communications. All rights reserved.
*
* Written by Dimitris Michailidis (dm@chelsio.com)
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
* release for licensing terms and conditions.
*/
#ifndef __CXGBE_T4_MSG_H
#define __CXGBE_T4_MSG_H
enum {
CPL_PASS_OPEN_REQ = 0x1,
CPL_PASS_ACCEPT_RPL = 0x2,
CPL_ACT_OPEN_REQ = 0x3,
CPL_SET_TCB = 0x4,
CPL_SET_TCB_FIELD = 0x5,
CPL_GET_TCB = 0x6,
CPL_PCMD = 0x7,
CPL_CLOSE_CON_REQ = 0x8,
CPL_CLOSE_LISTSRV_REQ = 0x9,
CPL_ABORT_REQ = 0xA,
CPL_ABORT_RPL = 0xB,
CPL_TX_DATA = 0xC,
CPL_RX_DATA_ACK = 0xD,
CPL_TX_PKT = 0xE,
CPL_RTE_DELETE_REQ = 0xF,
CPL_RTE_WRITE_REQ = 0x10,
CPL_RTE_READ_REQ = 0x11,
CPL_L2T_WRITE_REQ = 0x12,
CPL_L2T_READ_REQ = 0x13,
CPL_SMT_WRITE_REQ = 0x14,
CPL_SMT_READ_REQ = 0x15,
CPL_BARRIER = 0x18,
CPL_TID_RELEASE = 0x1A,
CPL_RX_MPS_PKT = 0x1B,
CPL_CLOSE_LISTSRV_RPL = 0x20,
CPL_ERROR = 0x21,
CPL_GET_TCB_RPL = 0x22,
CPL_L2T_WRITE_RPL = 0x23,
CPL_PASS_OPEN_RPL = 0x24,
CPL_ACT_OPEN_RPL = 0x25,
CPL_PEER_CLOSE = 0x26,
CPL_RTE_DELETE_RPL = 0x27,
CPL_RTE_WRITE_RPL = 0x28,
CPL_RX_URG_PKT = 0x29,
CPL_ABORT_REQ_RSS = 0x2B,
CPL_RX_URG_NOTIFY = 0x2C,
CPL_ABORT_RPL_RSS = 0x2D,
CPL_SMT_WRITE_RPL = 0x2E,
CPL_TX_DATA_ACK = 0x2F,
CPL_RX_PHYS_ADDR = 0x30,
CPL_PCMD_READ_RPL = 0x31,
CPL_CLOSE_CON_RPL = 0x32,
CPL_ISCSI_HDR = 0x33,
CPL_L2T_READ_RPL = 0x34,
CPL_RDMA_CQE = 0x35,
CPL_RDMA_CQE_READ_RSP = 0x36,
CPL_RDMA_CQE_ERR = 0x37,
CPL_RTE_READ_RPL = 0x38,
CPL_RX_DATA = 0x39,
CPL_SET_TCB_RPL = 0x3A,
CPL_RX_PKT = 0x3B,
CPL_PCMD_RPL = 0x3C,
CPL_HIT_NOTIFY = 0x3D,
CPL_PKT_NOTIFY = 0x3E,
CPL_RX_DDP_COMPLETE = 0x3F,
CPL_ACT_ESTABLISH = 0x40,
CPL_PASS_ESTABLISH = 0x41,
CPL_RX_DATA_DDP = 0x42,
CPL_SMT_READ_RPL = 0x43,
CPL_PASS_ACCEPT_REQ = 0x44,
CPL_RX2TX_PKT = 0x45,
CPL_RX_FCOE_DDP = 0x46,
CPL_FCOE_HDR = 0x47,
CPL_RDMA_READ_REQ = 0x60,
CPL_SET_LE_REQ = 0x80,
CPL_PASS_OPEN_REQ6 = 0x81,
CPL_ACT_OPEN_REQ6 = 0x83,
CPL_TX_DMA_ACK = 0xA0,
CPL_RDMA_TERMINATE = 0xA2,
CPL_RDMA_WRITE = 0xA4,
CPL_SGE_EGR_UPDATE = 0xA5,
CPL_SET_LE_RPL = 0xA6,
CPL_FW2_MSG = 0xA7,
CPL_FW2_PLD = 0xA8,
CPL_TRACE_PKT = 0xB0,
CPL_RX2TX_DATA = 0xB1,
CPL_FW4_MSG = 0xC0,
CPL_FW4_PLD = 0xC1,
CPL_FW4_ACK = 0xC3,
CPL_FW6_MSG = 0xE0,
CPL_FW6_PLD = 0xE1,
CPL_TX_PKT_LSO = 0xED,
CPL_TX_PKT_XT = 0xEE,
NUM_CPL_CMDS /* must be last and previous entries must be sorted */
};
enum CPL_error {
CPL_ERR_NONE = 0,
CPL_ERR_TCAM_PARITY = 1,
CPL_ERR_TCAM_FULL = 3,
CPL_ERR_BAD_LENGTH = 15,
CPL_ERR_BAD_ROUTE = 18,
CPL_ERR_CONN_RESET = 20,
CPL_ERR_CONN_EXIST = 22,
CPL_ERR_ARP_MISS = 23,
CPL_ERR_BAD_SYN = 24,
CPL_ERR_CONN_TIMEDOUT = 30,
CPL_ERR_XMIT_TIMEDOUT = 31,
CPL_ERR_PERSIST_TIMEDOUT = 32,
CPL_ERR_RTX_NEG_ADVICE = 35,
CPL_ERR_WAIT_ARP_RPL = 41,
CPL_ERR_ABORT_FAILED = 42,
CPL_ERR_IWARP_FLM = 50,
};
enum {
CPL_CONN_POLICY_AUTO = 0,
CPL_CONN_POLICY_ASK = 1,
};
enum {
ULP_MODE_NONE = 0,
ULP_MODE_ISCSI = 2,
ULP_MODE_RDMA = 4,
ULP_MODE_TCPDDP = 5,
ULP_MODE_FCOE = 6,
};
enum {
ULP_CRC_HEADER = 1 << 0,
};
enum {
};
enum {
CPL_ABORT_SEND_RST = 0,
};
enum { /* TX_PKT_XT checksum types */
TX_CSUM_TCP = 0,
TX_CSUM_UDP = 1,
TX_CSUM_CRC16 = 4,
TX_CSUM_CRC32 = 5,
TX_CSUM_CRC32C = 6,
TX_CSUM_FCOE = 7,
TX_CSUM_TCPIP = 8,
TX_CSUM_UDPIP = 9,
TX_CSUM_TCPIP6 = 10,
TX_CSUM_UDPIP6 = 11,
TX_CSUM_IP = 12,
};
enum { /* packet type in CPL_RX_PKT */
PKTYPE_XACT_UCAST = 0,
PKTYPE_HASH_UCAST = 1,
PKTYPE_XACT_MCAST = 2,
PKTYPE_HASH_MCAST = 3,
PKTYPE_PROMISC = 4,
PKTYPE_HPROMISC = 5,
PKTYPE_BCAST = 6
};
enum { /* DMAC type in CPL_RX_PKT */
};
enum { /* TCP congestion control algorithms */
};
enum { /* RSS hash type */
RSS_HASH_NONE = 0, /* no hash computed */
};
enum { /* LE commands */
LE_CMD_READ = 0x4,
LE_CMD_WRITE = 0xb
};
enum { /* LE request size */
LE_SZ_NONE = 0,
LE_SZ_33 = 1,
LE_SZ_66 = 2,
LE_SZ_132 = 3,
LE_SZ_264 = 4,
LE_SZ_528 = 5
};
union opcode_tid {
};
#define S_CPL_OPCODE 24
#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
#define G_TID(x) ((x) & 0xFFFFFF)
/* tid is assumed to be 24-bits */
/* extract the TID from a CPL command */
/* partitioning of TID fields that also carry a queue id */
#define S_TID_TID 0
#define M_TID_TID 0x3fff
#define S_TID_QID 14
#define M_TID_QID 0x3ff
union opcode_info {
};
struct tcp_options {
#if defined(__LITTLE_ENDIAN_BITFIELD)
__u8 :4;
__u8 :1;
#else
__u8 :1;
__u8 :4;
#endif
};
struct rss_header {
#if defined(__LITTLE_ENDIAN_BITFIELD)
#else
#endif
};
#define S_HASHTYPE 20
#define M_HASHTYPE 0x3
#define S_QNUM 0
#define M_QNUM 0xFFFF
#ifndef CHELSIO_FW
struct work_request_hdr {
};
/* wr_mid fields */
#define S_WR_LEN16 0
#define M_WR_LEN16 0xFF
#define V_WR_LEN16(x) ((x) << S_WR_LEN16)
/* wr_hi fields */
#define S_WR_OP 24
#define M_WR_OP 0xFF
#define WR_HDR_SIZE sizeof (struct work_request_hdr)
#define RSS_HDR
#else
#define WR_HDR
#define WR_HDR_SIZE 0
#endif
/* option 0 fields */
#define S_ACCEPT_MODE 0
#define M_ACCEPT_MODE 0x3
#define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE)
#define S_TX_CHAN 2
#define M_TX_CHAN 0x3
#define S_NO_CONG 4
#define S_DELACK 5
#define S_INJECT_TIMER 6
#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
#define S_NON_OFFLOAD 7
#define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
#define S_ULP_MODE 8
#define M_ULP_MODE 0xF
#define V_ULP_MODE(x) ((x) << S_ULP_MODE)
#define S_RCV_BUFSIZ 12
#define M_RCV_BUFSIZ 0x3FFU
#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
#define S_DSCP 22
#define M_DSCP 0x3F
#define S_SMAC_SEL 28
#define M_SMAC_SEL 0xFF
#define S_L2T_IDX 36
#define M_L2T_IDX 0xFFF
#define S_TCAM_BYPASS 48
#define S_NAGLE 49
#define S_WND_SCALE 50
#define M_WND_SCALE 0xF
#define S_KEEP_ALIVE 54
#define S_MAX_RT 55
#define M_MAX_RT 0xF
#define S_MAX_RT_OVERRIDE 59
#define S_MSS_IDX 60
#define M_MSS_IDX 0xF
/* option 1 fields */
#define S_SYN_RSS_ENABLE 0
#define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE)
#define S_SYN_RSS_USE_HASH 1
#define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH)
#define S_SYN_RSS_QUEUE 2
#define M_SYN_RSS_QUEUE 0x3FF
#define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE)
#define S_LISTEN_INTF 12
#define M_LISTEN_INTF 0xFF
#define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF)
#define S_LISTEN_FILTER 20
#define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER)
#define S_SYN_DEFENSE 21
#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
#define S_CONN_POLICY 22
#define M_CONN_POLICY 0x3
#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
/* option 2 fields */
#define S_RSS_QUEUE 0
#define M_RSS_QUEUE 0x3FF
#define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
#define S_RSS_QUEUE_VALID 10
#define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
#define S_RX_COALESCE_VALID 11
#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
#define S_RX_COALESCE 12
#define M_RX_COALESCE 0x3
#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
#define S_CONG_CNTRL 14
#define M_CONG_CNTRL 0x3
#define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
#define S_PACE 16
#define M_PACE 0x3
#define S_CONG_CNTRL_VALID 18
#define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
#define S_PACE_VALID 19
#define V_PACE_VALID(x) ((x) << S_PACE_VALID)
#define S_RX_FC_DISABLE 20
#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
#define S_RX_FC_DDP 21
#define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP)
#define S_RX_FC_VALID 22
#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
#define S_TX_QUEUE 23
#define M_TX_QUEUE 0x7
#define V_TX_QUEUE(x) ((x) << S_TX_QUEUE)
#define S_RX_CHANNEL 26
#define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
#define S_CCTRL_ECN 27
#define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
#define S_WND_SCALE_EN 28
#define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN)
#define S_TSTAMPS_EN 29
#define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
#define S_SACK_EN 30
struct cpl_pass_open_req {
union opcode_tid ot;
};
struct cpl_pass_open_req6 {
union opcode_tid ot;
};
struct cpl_pass_open_rpl {
union opcode_tid ot;
};
struct cpl_pass_establish {
union opcode_tid ot;
};
/* cpl_pass_establish.tos_stid fields */
#define S_PASS_OPEN_TID 0
#define M_PASS_OPEN_TID 0xFFFFFF
#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
#define S_PASS_OPEN_TOS 24
#define M_PASS_OPEN_TOS 0xFF
#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
struct cpl_pass_accept_req {
union opcode_tid ot;
struct tcp_options tcpopt;
};
/* cpl_pass_accept_req.hdr_len fields */
#define S_SYN_RX_CHAN 0
#define M_SYN_RX_CHAN 0xF
#define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
#define S_TCP_HDR_LEN 10
#define M_TCP_HDR_LEN 0x3F
#define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
#define S_IP_HDR_LEN 16
#define M_IP_HDR_LEN 0x3FF
#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
#define S_ETH_HDR_LEN 26
#define M_ETH_HDR_LEN 0x1F
#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
/* cpl_pass_accept_req.l2info fields */
#define S_SYN_MAC_IDX 0
#define M_SYN_MAC_IDX 0x1FF
#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
#define S_SYN_XACT_MATCH 9
#define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
#define S_SYN_INTF 12
#define M_SYN_INTF 0xF
#define V_SYN_INTF(x) ((x) << S_SYN_INTF)
struct cpl_pass_accept_rpl {
union opcode_tid ot;
};
struct cpl_act_open_req {
union opcode_tid ot;
};
struct cpl_act_open_req6 {
union opcode_tid ot;
};
struct cpl_act_open_rpl {
union opcode_tid ot;
};
/* cpl_act_open_rpl.atid_status fields */
#define S_AOPEN_STATUS 0
#define M_AOPEN_STATUS 0xFF
#define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS)
#define S_AOPEN_ATID 8
#define M_AOPEN_ATID 0xFFFFFF
#define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID)
struct cpl_act_establish {
union opcode_tid ot;
};
struct cpl_get_tcb {
union opcode_tid ot;
};
/* cpl_get_tcb.reply_ctrl fields */
#define S_QUEUENO 0
#define M_QUEUENO 0x3FF
#define S_REPLY_CHAN 14
#define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
#define S_NO_REPLY 15
#define V_NO_REPLY(x) ((x) << S_NO_REPLY)
struct cpl_get_tcb_rpl {
union opcode_tid ot;
};
struct cpl_set_tcb {
union opcode_tid ot;
};
struct cpl_set_tcb_field {
union opcode_tid ot;
};
/* cpl_set_tcb_field.word_cookie fields */
#define S_WORD 0
#define M_WORD 0x1F
#define S_COOKIE 5
#define M_COOKIE 0x7
struct cpl_set_tcb_rpl {
union opcode_tid ot;
};
struct cpl_close_con_req {
union opcode_tid ot;
};
struct cpl_close_con_rpl {
union opcode_tid ot;
};
struct cpl_close_listsvr_req {
union opcode_tid ot;
};
/* additional cpl_close_listsvr_req.reply_ctrl field */
#define S_LISTSVR_IPV6 14
#define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
struct cpl_close_listsvr_rpl {
union opcode_tid ot;
};
struct cpl_abort_req_rss {
union opcode_tid ot;
};
struct cpl_abort_req {
union opcode_tid ot;
};
struct cpl_abort_rpl_rss {
union opcode_tid ot;
};
struct cpl_abort_rpl {
union opcode_tid ot;
};
struct cpl_peer_close {
union opcode_tid ot;
};
struct cpl_tid_release {
union opcode_tid ot;
};
struct tx_data_wr {
};
/* tx_data_wr.flags fields */
#define S_TX_ACK_PAGES 21
#define M_TX_ACK_PAGES 0x7
#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
/* tx_data_wr.param fields */
#define S_TX_PORT 0
#define M_TX_PORT 0x7
#define S_TX_MSS 4
#define M_TX_MSS 0xF
#define S_TX_QOS 8
#define M_TX_QOS 0xFF
#define S_TX_SNDBUF 16
#define M_TX_SNDBUF 0xFFFF
#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
struct cpl_tx_data {
union opcode_tid ot;
};
/* cpl_tx_data.flags fields */
#define S_TX_PROXY 5
#define V_TX_PROXY(x) ((x) << S_TX_PROXY)
#define S_TX_ULP_SUBMODE 6
#define M_TX_ULP_SUBMODE 0xF
#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
#define S_TX_ULP_MODE 10
#define M_TX_ULP_MODE 0xF
#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
#define S_TX_SHOVE 14
#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
#define S_TX_MORE 15
#define S_TX_URG 16
#define S_TX_FLUSH 17
#define V_TX_FLUSH(x) ((x) << S_TX_FLUSH)
#define S_TX_SAVE 18
#define S_TX_TNL 19
/* additional tx_data_wr.flags fields */
#define S_TX_CPU_IDX 0
#define M_TX_CPU_IDX 0x3F
#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
#define S_TX_CLOSE 17
#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
#define S_TX_INIT 18
#define S_TX_IMM_ACK 19
#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
#define S_TX_IMM_DMA 20
#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
struct cpl_tx_data_ack {
union opcode_tid ot;
};
struct cpl_wr_ack { /* TODO */
union opcode_tid ot;
};
struct cpl_tx_pkt_core {
};
struct cpl_tx_pkt {
struct cpl_tx_pkt_core c;
};
#define cpl_tx_pkt_xt cpl_tx_pkt
/* cpl_tx_pkt_core.ctrl0 fields */
#define S_TXPKT_VF 0
#define M_TXPKT_VF 0xFF
#define V_TXPKT_VF(x) ((x) << S_TXPKT_VF)
#define S_TXPKT_PF 8
#define M_TXPKT_PF 0x7
#define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
#define S_TXPKT_VF_VLD 11
#define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
#define S_TXPKT_OVLAN_IDX 12
#define M_TXPKT_OVLAN_IDX 0xF
#define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
#define S_TXPKT_INTF 16
#define M_TXPKT_INTF 0xF
#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
#define S_TXPKT_SPECIAL_STAT 20
#define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
#define S_TXPKT_INS_OVLAN 21
#define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
#define S_TXPKT_STAT_DIS 22
#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
#define S_TXPKT_LOOPBACK 23
#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
#define S_TXPKT_OPCODE 24
#define M_TXPKT_OPCODE 0xFF
#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
/* cpl_tx_pkt_core.ctrl1 fields */
#define S_TXPKT_SA_IDX 0
#define M_TXPKT_SA_IDX 0xFFF
#define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX)
#define S_TXPKT_CSUM_END 12
#define M_TXPKT_CSUM_END 0xFF
#define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END)
#define S_TXPKT_CSUM_START 20
#define M_TXPKT_CSUM_START 0x3FF
#define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START)
#define S_TXPKT_IPHDR_LEN 20
#define M_TXPKT_IPHDR_LEN 0x3FFF
#define S_TXPKT_CSUM_LOC 30
#define M_TXPKT_CSUM_LOC 0x3FF
#define S_TXPKT_ETHHDR_LEN 34
#define M_TXPKT_ETHHDR_LEN 0x3F
#define S_TXPKT_CSUM_TYPE 40
#define M_TXPKT_CSUM_TYPE 0xF
#define S_TXPKT_VLAN 44
#define M_TXPKT_VLAN 0xFFFF
#define S_TXPKT_VLAN_VLD 60
#define S_TXPKT_IPSEC 61
#define S_TXPKT_IPCSUM_DIS 62
#define S_TXPKT_L4CSUM_DIS 63
struct cpl_tx_pkt_lso {
/* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
};
/* cpl_tx_pkt_lso.lso_ctrl fields */
#define S_LSO_TCPHDR_LEN 0
#define M_LSO_TCPHDR_LEN 0xF
#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
#define S_LSO_IPHDR_LEN 4
#define M_LSO_IPHDR_LEN 0xFFF
#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
#define S_LSO_ETHHDR_LEN 16
#define M_LSO_ETHHDR_LEN 0xF
#define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
#define S_LSO_IPV6 20
#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
#define S_LSO_OFLD_ENCAP 21
#define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP)
#define S_LSO_LAST_SLICE 22
#define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
#define S_LSO_FIRST_SLICE 23
#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
#define S_LSO_OPCODE 24
#define M_LSO_OPCODE 0xFF
#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
/* cpl_tx_pkt_lso.mss fields */
#define S_LSO_MSS 0
#define M_LSO_MSS 0x3FFF
#define S_LSO_IPID_SPLIT 15
#define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)
struct cpl_tx_pkt_coalesce {
};
struct tx_pkt_coalesce_wr {
#if !(defined C99_NOT_SUPPORTED)
struct cpl_tx_pkt_coalesce cpl[];
#endif
};
struct mngt_pktsched_wr {
};
struct cpl_iscsi_hdr_no_rss {
union opcode_tid ot;
};
struct cpl_iscsi_hdr {
union opcode_tid ot;
};
/* cpl_iscsi_hdr.pdu_len_ddp fields */
#define S_ISCSI_PDU_LEN 0
#define M_ISCSI_PDU_LEN 0x7FFF
#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
#define S_ISCSI_DDP 15
#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
struct cpl_rx_data {
union opcode_tid ot;
#if defined(__LITTLE_ENDIAN_BITFIELD)
__u8 :3;
#else
__u8 :3;
#endif
};
struct cpl_fcoe_hdr {
union opcode_tid ot;
};
struct cpl_rx_urg_notify {
union opcode_tid ot;
};
struct cpl_rx_urg_pkt {
union opcode_tid ot;
};
struct cpl_rx_data_ack {
union opcode_tid ot;
};
/* cpl_rx_data_ack.ack_seq fields */
#define S_RX_CREDITS 0
#define M_RX_CREDITS 0x3FFFFFF
#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
#define S_RX_MODULATE_TX 26
#define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX)
#define S_RX_MODULATE_RX 27
#define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX)
#define S_RX_FORCE_ACK 28
#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
#define S_RX_DACK_MODE 29
#define M_RX_DACK_MODE 0x3
#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
#define S_RX_DACK_CHANGE 31
#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
struct cpl_rx_ddp_complete {
union opcode_tid ot;
};
struct cpl_rx_data_ddp {
union opcode_tid ot;
union {
} u;
};
struct cpl_rx_fcoe_ddp {
union opcode_tid ot;
};
/* cpl_rx_{data,fcoe}_ddp.ddpvld fields */
#define S_DDP_VALID 15
#define M_DDP_VALID 0x1FFFF
#define V_DDP_VALID(x) ((x) << S_DDP_VALID)
#define S_DDP_PPOD_MISMATCH 15
#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
#define S_DDP_PDU 16
#define S_DDP_LLIMIT_ERR 17
#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
#define S_DDP_PPOD_PARITY_ERR 18
#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
#define S_DDP_PADDING_ERR 19
#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
#define S_DDP_HDRCRC_ERR 20
#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
#define S_DDP_DATACRC_ERR 21
#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
#define S_DDP_INVALID_TAG 22
#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
#define S_DDP_ULIMIT_ERR 23
#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
#define S_DDP_OFFSET_ERR 24
#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
#define S_DDP_COLOR_ERR 25
#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
#define S_DDP_TID_MISMATCH 26
#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
#define S_DDP_INVALID_PPOD 27
#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
#define S_DDP_ULP_MODE 28
#define M_DDP_ULP_MODE 0xF
#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
/* cpl_rx_{data,fcoe}_ddp.ddp_report fields */
#define S_DDP_OFFSET 0
#define M_DDP_OFFSET 0xFFFFFF
#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
#define S_DDP_DACK_MODE 24
#define M_DDP_DACK_MODE 0x3
#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
#define S_DDP_BUF_IDX 26
#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
#define S_DDP_URG 27
#define S_DDP_PSH 28
#define S_DDP_BUF_COMPLETE 29
#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
#define S_DDP_BUF_TIMED_OUT 30
#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
#define S_DDP_INV 31
struct cpl_rx_pkt {
#if defined(__LITTLE_ENDIAN_BITFIELD)
#else
#endif
};
/* rx_pkt.l2info fields */
#define S_RX_ETHHDR_LEN 0
#define M_RX_ETHHDR_LEN 0x1F
#define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
#define S_RX_PKTYPE 5
#define M_RX_PKTYPE 0x7
#define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
#define S_RX_MACIDX 8
#define M_RX_MACIDX 0x1FF
#define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
#define S_RX_DATYPE 18
#define M_RX_DATYPE 0x3
#define V_RX_DATYPE(x) ((x) << S_RX_DATYPE)
#define S_RXF_PSH 20
#define S_RXF_SYN 21
#define S_RXF_UDP 22
#define S_RXF_TCP 23
#define S_RXF_IP 24
#define S_RXF_IP6 25
#define S_RXF_SYN_COOKIE 26
#define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE)
#define S_RXF_FCOE 26
#define V_RXF_FCOE(x) ((x) << S_RXF_FCOE)
#define S_RXF_LRO 27
#define S_RX_CHAN 28
#define M_RX_CHAN 0xF
/* rx_pkt.hdr_len fields */
#define S_RX_TCPHDR_LEN 0
#define M_RX_TCPHDR_LEN 0x3F
#define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
#define S_RX_IPHDR_LEN 6
#define M_RX_IPHDR_LEN 0x3FF
#define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
/* rx_pkt.err_vec fields */
#define S_RXERR_OR 0
#define V_RXERR_OR(x) ((x) << S_RXERR_OR)
#define S_RXERR_MAC 1
#define V_RXERR_MAC(x) ((x) << S_RXERR_MAC)
#define S_RXERR_IPVERS 2
#define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS)
#define S_RXERR_FRAG 3
#define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG)
#define S_RXERR_ATTACK 4
#define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK)
#define S_RXERR_ETHHDR_LEN 5
#define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN)
#define S_RXERR_IPHDR_LEN 6
#define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN)
#define S_RXERR_TCPHDR_LEN 7
#define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN)
#define S_RXERR_PKT_LEN 8
#define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN)
#define S_RXERR_TCP_OPT 9
#define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT)
#define S_RXERR_IPCSUM 12
#define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM)
#define S_RXERR_CSUM 13
#define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM)
#define S_RXERR_PING 14
#define V_RXERR_PING(x) ((x) << S_RXERR_PING)
struct cpl_trace_pkt {
#if defined(__LITTLE_ENDIAN_BITFIELD)
__u8 :6;
#else
__u8 :6;
#endif
};
struct cpl_rte_delete_req {
union opcode_tid ot;
};
/* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */
#define S_RTE_REQ_LUT_IX 8
#define M_RTE_REQ_LUT_IX 0x7FF
#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
#define S_RTE_REQ_LUT_BASE 19
#define M_RTE_REQ_LUT_BASE 0x7FF
#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
#define S_RTE_READ_REQ_SELECT 31
#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
struct cpl_rte_delete_rpl {
union opcode_tid ot;
};
struct cpl_rte_write_req {
union opcode_tid ot;
};
/* cpl_rte_write_req.write_sel fields */
#define S_RTE_WR_L2TIDX 31
#define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX)
#define S_RTE_WR_FADDR 30
#define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR)
/* cpl_rte_write_req.lut_params fields */
#define S_RTE_WR_LUT_IX 10
#define M_RTE_WR_LUT_IX 0x7FF
#define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX)
#define S_RTE_WR_LUT_BASE 21
#define M_RTE_WR_LUT_BASE 0x7FF
#define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE)
struct cpl_rte_write_rpl {
union opcode_tid ot;
};
struct cpl_rte_read_req {
union opcode_tid ot;
};
struct cpl_rte_read_rpl {
union opcode_tid ot;
#if defined(__LITTLE_ENDIAN_BITFIELD)
__u32 :30;
#else
__u32 :30;
#endif
};
struct cpl_l2t_write_req {
union opcode_tid ot;
};
/* cpl_l2t_write_req.params fields */
#define S_L2T_W_INFO 2
#define M_L2T_W_INFO 0x3F
#define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
#define S_L2T_W_PORT 8
#define M_L2T_W_PORT 0xF
#define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
#define S_L2T_W_NOREPLY 15
#define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
struct cpl_l2t_write_rpl {
union opcode_tid ot;
};
struct cpl_l2t_read_req {
union opcode_tid ot;
};
struct cpl_l2t_read_rpl {
union opcode_tid ot;
#if defined(__LITTLE_ENDIAN_BITFIELD)
__u8 :4;
#else
__u8 :4;
#endif
};
struct cpl_smt_write_req {
union opcode_tid ot;
};
/* cpl_smt_{read,write}_req.params fields */
#define S_SMTW_OVLAN_IDX 16
#define M_SMTW_OVLAN_IDX 0xF
#define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX)
#define S_SMTW_IDX 20
#define M_SMTW_IDX 0x7F
#define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
#define S_SMTW_NORPL 31
#define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
/* cpl_smt_{read,write}_req.pfvf? fields */
#define S_SMTW_VF 0
#define M_SMTW_VF 0xFF
#define S_SMTW_PF 8
#define M_SMTW_PF 0x7
#define S_SMTW_VF_VLD 11
#define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
struct cpl_smt_write_rpl {
union opcode_tid ot;
};
struct cpl_smt_read_req {
union opcode_tid ot;
};
struct cpl_smt_read_rpl {
union opcode_tid ot;
};
struct cpl_barrier {
};
/* cpl_barrier.chan_map fields */
#define S_CHAN_MAP 4
#define M_CHAN_MAP 0xF
#define V_CHAN_MAP(x) ((x) << S_CHAN_MAP)
struct cpl_error {
union opcode_tid ot;
};
struct cpl_hit_notify {
union opcode_tid ot;
};
struct cpl_pkt_notify {
union opcode_tid ot;
};
/* cpl_{hit,pkt}_notify.info fields */
#define S_NTFY_MAC_IDX 0
#define M_NTFY_MAC_IDX 0x1FF
#define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX)
#define S_NTFY_INTF 10
#define M_NTFY_INTF 0xF
#define V_NTFY_INTF(x) ((x) << S_NTFY_INTF)
#define S_NTFY_TCPHDR_LEN 14
#define M_NTFY_TCPHDR_LEN 0xF
#define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN)
#define S_NTFY_IPHDR_LEN 18
#define M_NTFY_IPHDR_LEN 0x1FF
#define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN)
#define S_NTFY_ETHHDR_LEN 27
#define M_NTFY_ETHHDR_LEN 0x1F
#define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN)
struct cpl_rdma_terminate {
union opcode_tid ot;
};
struct cpl_set_le_req {
union opcode_tid ot;
};
/* cpl_set_le_req.reply_ctrl additional fields */
#define S_LE_REQ_IP6 13
#define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
/* cpl_set_le_req.params fields */
#define S_LE_CHAN 0
#define M_LE_CHAN 0x3
#define S_LE_OFFSET 5
#define M_LE_OFFSET 0x7
#define V_LE_OFFSET(x) ((x) << S_LE_OFFSET)
#define S_LE_MORE 8
#define S_LE_REQSIZE 9
#define M_LE_REQSIZE 0x7
#define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE)
#define S_LE_REQCMD 12
#define M_LE_REQCMD 0xF
#define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
struct cpl_set_le_rpl {
union opcode_tid ot;
};
/* cpl_set_le_rpl.info fields */
#define S_LE_RSPCMD 0
#define M_LE_RSPCMD 0xF
#define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD)
#define S_LE_RSPSIZE 4
#define M_LE_RSPSIZE 0x7
#define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE)
#define S_LE_RSPTYPE 7
#define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE)
struct cpl_sge_egr_update {
};
/* cpl_sge_egr_update.ot fields */
#define S_EGR_QID 0
#define M_EGR_QID 0x1FFFF
struct cpl_fw2_pld {
};
struct cpl_fw4_pld {
};
struct cpl_fw6_pld {
};
struct cpl_fw2_msg {
union opcode_info oi;
};
struct cpl_fw4_msg {
};
struct cpl_fw4_ack {
union opcode_tid ot;
};
enum {
};
struct cpl_fw6_msg {
};
/* cpl_fw6_msg.type values */
enum {
FW6_TYPE_CMD_RPL = 0,
};
/* ULP_TX opcodes */
enum {
ULP_TX_MEM_READ = 2,
ULP_TX_MEM_WRITE = 3,
ULP_TX_PKT = 4
};
enum {
ULP_TX_SC_NOOP = 0x80,
ULP_TX_SC_IMM = 0x81,
ULP_TX_SC_DSGL = 0x82,
ULP_TX_SC_ISGL = 0x83
};
#define S_ULPTX_CMD 24
#define M_ULPTX_CMD 0xFF
#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
#define S_ULPTX_LEN16 0
#define M_ULPTX_LEN16 0xFF
#define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16)
#define S_ULP_TX_SC_MORE 23
#define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
struct ulptx_sge_pair {
};
struct ulptx_sgl {
#if !(defined C99_NOT_SUPPORTED)
struct ulptx_sge_pair sge[];
#endif
};
struct ulptx_isge {
};
struct ulptx_isgl {
#if !(defined C99_NOT_SUPPORTED)
struct ulptx_isge sge[];
#endif
};
struct ulptx_idata {
};
#define S_ULPTX_NSGE 0
#define M_ULPTX_NSGE 0xFFFF
#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
struct ulp_mem_io {
};
/* additional ulp_mem_io.cmd fields */
#define S_ULP_MEMIO_ORDER 23
#define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
/* ulp_mem_io.lock_addr fields */
#define S_ULP_MEMIO_ADDR 0
#define M_ULP_MEMIO_ADDR 0x7FFFFFF
#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
#define S_ULP_MEMIO_LOCK 31
#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
/* ulp_mem_io.dlen fields */
#define S_ULP_MEMIO_DATA_LEN 0
#define M_ULP_MEMIO_DATA_LEN 0x1F
#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
struct ulp_txpkt {
};
/* ulp_txpkt.cmd_dest fields */
#define S_ULP_TXPKT_DEST 16
#define M_ULP_TXPKT_DEST 0x3
#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
#define S_ULP_TXPKT_FID 4
#define M_ULP_TXPKT_FID 0x7ff
#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
#endif /* __CXGBE_T4_MSG_H */