t4_hw.h revision 56b2bdd1f04d465cfe4a95b88ae5cba5884154e4
/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
*/
/*
* This file is part of the Chelsio T4 Ethernet driver.
*
* Copyright (C) 2009-2013 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
* release for licensing terms and conditions.
*/
#ifndef __CXGBE_T4_HW_H
#define __CXGBE_T4_HW_H
#include "osdep.h"
enum {
/* components */
};
enum {
};
enum {
};
/* SGE context types */
enum {
};
struct sge_qstat { /* data written to SGE queue status entries */
};
#define S_QSTAT_PIDX 0
#define M_QSTAT_PIDX 0xffff
#define S_QSTAT_CIDX 16
#define M_QSTAT_CIDX 0xffff
/*
* Structure for last 128 bits of response descriptors
*/
struct rsp_ctrl {
union {
} u;
};
#define S_RSPD_NEWBUF 31
#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
#define S_RSPD_LEN 0
#define M_RSPD_LEN 0x7fffffff
#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
#define S_RSPD_QID S_RSPD_LEN
#define M_RSPD_QID M_RSPD_LEN
#define V_RSPD_QID(x) V_RSPD_LEN(x)
#define G_RSPD_QID(x) G_RSPD_LEN(x)
#define S_RSPD_GEN 7
#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
#define S_RSPD_QOVFL 6
#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
#define S_RSPD_TYPE 4
#define M_RSPD_TYPE 0x3
#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
/* Rx queue interrupt deferral fields: counter enable and timer index */
#define S_QINTR_CNT_EN 0
#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
#define S_QINTR_TIMER_IDX 1
#define M_QINTR_TIMER_IDX 0x7
#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
/* # of pages a pagepod can hold without needing another pagepod */
#define PPOD_PAGES 4U
struct pagepod {
};
#define S_PPOD_COLOR 0
#define M_PPOD_COLOR 0x3F
#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
#define S_PPOD_TAG 6
#define M_PPOD_TAG 0xFFFFFF
#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
#define S_PPOD_PGSZ 30
#define M_PPOD_PGSZ 0x3
#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
#define S_PPOD_TID 32
#define M_PPOD_TID 0xFFFFFF
#define S_PPOD_VALID 56
#define S_PPOD_LEN 32
#define M_PPOD_LEN 0xFFFFFFFF
#define S_PPOD_OFST 0
#define M_PPOD_OFST 0xFFFFFFFF
#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
/*
* Flash layout.
*/
enum {
/*
* Various Expansion-ROM boot images, etc.
*/
FLASH_EXP_ROM_NSECS = 6,
/*
* iSCSI Boot Firmware Table (iBFT) and other driver-related
* parameters ...
*/
FLASH_IBFT_START_SEC = 6,
FLASH_IBFT_NSECS = 1,
/*
* Boot configuration data.
*/
FLASH_BOOTCFG_NSECS = 1,
/*
* Location of firmware image in FLASH.
*/
FLASH_FW_START_SEC = 8,
FLASH_FW_NSECS = 8,
/*
* iSCSI persistent/crash information.
*/
/*
* FCoE persistent/crash information.
*/
/*
* Location of Firmware Configuration File in FLASH. Since the FPGA
* "FLASH" is smaller we need to store the Configuration File in a
* different location -- which will overlap the end of the firmware
* image if firmware ever gets that large ...
*/
FLASH_CFG_START_SEC = 31,
FLASH_CFG_NSECS = 1,
FLASH_FPGA_CFG_START_SEC = 15,
/*
* Sectors 32-63 are reserved for FLASH failover.
*/
};
#endif /* __CXGBE_T4_HW_H */