sge.h revision d39a76e7b087a3d0927cbe6898dc0a6770fa6c68
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* This file is part of the Chelsio T1 Ethernet driver.
*
* Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
*/
#ifndef _CHELSIO_SGE_H
#define _CHELSIO_SGE_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include "osdep.h"
#define MBLK_MAX 8
#define spin_lock mutex_enter
#define spin_unlock mutex_exit
#define atomic_sub(a, b) atomic_add_32(b, -(a))
#define atomic_add(a, b) atomic_add_32(b, (a))
#define atomic_read(a) (a)
#define atomic_set(a, b) (*(a) = b)
#define spinlock_t kmutex_t
#define dma_addr_t uint64_t
#define wmb() membar_producer()
#define unlikely(a) (a)
#define likely(a) (a)
#define SGE_CMDQ_N 2
#define SGE_FREELQ_N 2
#ifdef CONFIG_CHELSIO_T1_OFFLOAD
#define SGE_CMDQ0_E_N 4096
#define SGE_CMDQ1_E_N 128
#define SGE_FREELQ0_E_N 2048
#define SGE_FREELQ1_E_N 1024
#else
#define SGE_CMDQ0_E_N 2048
#define SGE_CMDQ1_E_N 128
#define SGE_FREELQ0_E_N 4096
#define SGE_FREELQ1_E_N 1024
#endif /* CONFIG_CHELSIO_T1_OFFLOAD */
#define SGE_BATCH_THRESH 16
#define SGE_INTR_BUCKETSIZE 100
#define SGE_INTR_MAXBUCKETS 11
#define SGE_INTRTIMER0 1
#define SGE_INTRTIMER1 30
#define SGE_INTRTIMER_NRES 10000
#define SGE_RX_COPY_THRESHOLD 256
#define SGE_RX_OFFSET 2
#ifdef CONFIG_CHELSIO_T1_OFFLOAD
#else
#endif
/*
* CPL5 Defines
*/
#define FLITSTOBYTES 8
#define CPL_FORMAT_0_SIZE 8
#define CPL_FORMAT_1_SIZE 16
#define CPL_FORMAT_2_SIZE 24
#define CPL_FORMAT_3_SIZE 32
#define CPL_FORMAT_4_SIZE 40
#define CPL_FORMAT_5_SIZE 48
#define TID_MASK 0xffffff
#define SZ_CPL_RX_PKT CPL_FORMAT_0_SIZE
#if BYTE_ORDER == BIG_ENDIAN
typedef struct {
typedef struct {
#endif
typedef CmdQueueEntry cmdQ_e;
#if BYTE_ORDER == BIG_ENDIAN
typedef struct {
typedef struct {
#endif
typedef ResponseQueueEntry respQ_e;
#if BYTE_ORDER == BIG_ENDIAN
typedef struct {
} FLQueueEntry;
typedef struct {
} FLQueueEntry;
#endif
typedef FLQueueEntry freelQ_e;
/*
* Command QUEUE meta entry format.
*/
typedef struct cmdQ_ce {
void *ce_mp; /* head mblk of pkt */
} cmdQ_ce_t;
/*
* command queue control structure
*/
typedef struct cmdQ {
} cmdQ_t;
/*
* free list queue control structure
*/
typedef struct freelQ {
} freelQ_t;
/*
* response queue control structure
*/
typedef struct respQ {
} reapQ_t;
struct sge_intr_counts {
#ifdef SUN_KSTATS
#endif
};
#ifdef SUN_KSTATS
typedef struct sge_intr_counts *p_ch_stats_t;
/*
* Driver maintained kernel statistics.
*/
typedef struct _ch_kstat_t {
/*
*/
} ch_kstat_t;
typedef ch_kstat_t *p_ch_kstat_t;
#endif
typedef struct _pesge {
struct sge_intr_counts intr_cnt;
#ifdef SUN_KSTATS
#endif
void *pskb;
int do_udp_csum;
int do_tcp_csum;
} _pesge;
/*
* ce_flg flag values
*/
#define DH_DMA 1
#define DH_DVMA 2
#define DH_TOE 3
#define DH_ARP 8
typedef struct freelQ_ce {
void *fe_mp; /* head mblk of pkt */
} freelQ_ce_t;
extern int sge_data_in(pesge *);
extern int t1_sge_intr_error_handler(pesge*);
extern int t1_sge_intr_enable(pesge*);
extern int t1_sge_intr_disable(pesge*);
extern int t1_sge_intr_clear(pesge*);
extern void sge_add_fake_arp(pesge *, void *);
/*
* Default SGE settings
*/
#define SGE_CMDQ0_CNT (512)
#define SGE_FLQ0_CNT (512)
#define SGE_RESPQ_CNT (1024)
/*
* the structures below were taken from cpl5_cmd.h. It turns out that there
* is a number of #includes that causes build problems. For now, we're
* putting a private copy here. When the sge code is made common, then this
* problem will need to be resolved.
*/
union opcode_tid {
};
/*
* We want this header's alignment to be no more stringent than 2-byte aligned.
* All fields are u8 or u16 except for the length. However that field is not
* used so we break it into 2 16-bit parts to easily meet our alignment needs.
*/
struct cpl_tx_pkt {
#if BYTE_ORDER == BIG_ENDIAN
#else
#endif
};
#define CPL_TX_PKT 0xb2
#define SZ_CPL_TX_PKT CPL_FORMAT_0_SIZE
struct cpl_rx_data {
union opcode_tid ot;
};
struct cpl_rx_pkt {
#if BYTE_ORDER == LITTLE_ENDIAN
#else
#endif
};
#ifdef __cplusplus
}
#endif
#endif /* _CHELSIO_SGE_H */