d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Gigabit MII registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* 1000Base-T control register fields */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* 1000Base-T status register fields */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Marvell PHY interrupt status bits. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Marvell PHY specific registers. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* PHY specific control register fields */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Extended PHY specific control register fields */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* PHY specific status register fields */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)