espi.c revision d39a76e7b087a3d0927cbe6898dc0a6770fa6c68
1N/A/*
1N/A * CDDL HEADER START
1N/A *
1N/A * The contents of this file are subject to the terms of the
1N/A * Common Development and Distribution License (the "License").
1N/A * You may not use this file except in compliance with the License.
1N/A *
1N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
1N/A * or http://www.opensolaris.org/os/licensing.
1N/A * See the License for the specific language governing permissions
1N/A * and limitations under the License.
1N/A *
1N/A * When distributing Covered Code, include this CDDL HEADER in each
1N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1N/A * If applicable, add the following below this CDDL HEADER, with the
1N/A * fields enclosed by brackets "[]" replaced with your own identifying
1N/A * information: Portions Copyright [yyyy] [name of copyright owner]
1N/A *
1N/A * CDDL HEADER END
1N/A */
1N/A
1N/A/*
1N/A * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
1N/A */
1N/A
1N/A#pragma ident "%Z%%M% %I% %E% SMI" /* espi.c */
1N/A
1N/A#include "common.h"
1N/A#include "regs.h"
1N/A#include "espi.h"
1N/A
1N/Astruct peespi {
1N/A adapter_t *adapter;
1N/A struct espi_intr_counts intr_cnt;
1N/A u32 misc_ctrl;
1N/A SPINLOCK lock;
1N/A};
1N/A
1N/A#define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \
1N/A F_RAMPARITYERR | F_DIP2PARITYERR)
1N/A#define MON_MASK (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \
1N/A | F_MONITORED_INTERFACE)
1N/A
1N/A#define TRICN_CNFG 14
1N/A#define TRICN_CMD_READ 0x11
1N/A#define TRICN_CMD_WRITE 0x21
1N/A#define TRICN_CMD_ATTEMPTS 10
1N/A
1N/Astatic int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
1N/A int ch_addr, int reg_offset, u32 wr_data)
1N/A{
1N/A int busy;
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) |
1N/A V_REGISTER_OFFSET(reg_offset) |
1N/A V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
1N/A V_BUNDLE_ADDR(bundle_addr) |
1N/A V_SPI4_COMMAND(TRICN_CMD_WRITE));
1N/A t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
1N/A
1N/A busy = t1_wait_op_done(adapter, A_ESPI_GOSTAT, F_ESPI_CMD_BUSY, 0,
1N/A TRICN_CMD_ATTEMPTS, 0);
1N/A
1N/A if (busy)
1N/A CH_ERR("%s: TRICN write timed out\n", adapter_name(adapter));
1N/A
1N/A return busy;
1N/A}
1N/A
1N/A#if 0
1N/Astatic int tricn_read(adapter_t *adapter, int bundle_addr, int module_addr,
1N/A int ch_addr, int reg_offset, u8 *rd_data)
1N/A{
1N/A int busy, attempts = TRICN_CMD_ATTEMPTS;
1N/A u32 status;
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
1N/A V_REGISTER_OFFSET(reg_offset) |
1N/A V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
1N/A V_BUNDLE_ADDR(bundle_addr) |
1N/A V_SPI4_COMMAND(TRICN_CMD_READ));
1N/A t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
1N/A
1N/A do {
1N/A status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);
1N/A busy = status & F_ESPI_CMD_BUSY;
1N/A } while (busy && --attempts);
1N/A
1N/A if (busy)
1N/A CH_ERR("%s: TRICN read timed out\n", adapter_name(adapter));
1N/A else
1N/A *rd_data = G_READ_DATA(status);
1N/A return busy;
1N/A}
1N/A#endif
1N/A
1N/Astatic int tricn_init(adapter_t *adapter)
1N/A{
1N/A int i, sme = 1;
1N/A
1N/A if (!(t1_read_reg_4(adapter, A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
1N/A CH_ERR("%s: ESPI clock not ready\n", adapter_name(adapter));
1N/A return (-1);
1N/A }
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST);
1N/A
1N/A if (sme) {
1N/A (void) tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
1N/A (void) tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
1N/A (void) tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
1N/A }
1N/A for (i=1; i<= 8; i++) (void) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
1N/A for (i=1; i<= 2; i++) (void) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
1N/A for (i=1; i<= 3; i++) (void) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
1N/A (void) tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
1N/A (void) tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
1N/A (void) tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
1N/A (void) tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
1N/A (void) tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST);
1N/A
1N/A return 0;
1N/A}
1N/A
1N/Avoid t1_espi_intr_enable(struct peespi *espi)
1N/A{
1N/A u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
1N/A
1N/A /*
1N/A * Cannot enable ESPI interrupts on T1B because HW asserts the
1N/A * interrupt incorrectly, namely the driver gets ESPI interrupts
1N/A * but no data is actually dropped (can verify this reading the ESPI
1N/A * drop registers). Also, once the ESPI interrupt is asserted it
1N/A * cannot be cleared (HW bug).
1N/A */
1N/A enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
1N/A t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable);
1N/A t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI);
1N/A}
1N/A
1N/Avoid t1_espi_intr_clear(struct peespi *espi)
1N/A{
1N/A (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
1N/A t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff);
1N/A t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI);
1N/A}
1N/A
1N/Avoid t1_espi_intr_disable(struct peespi *espi)
1N/A{
1N/A u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
1N/A
1N/A t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, 0);
1N/A t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI);
1N/A}
1N/A
1N/Aint t1_espi_intr_handler(struct peespi *espi)
1N/A{
1N/A u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS);
1N/A
1N/A if (status & F_DIP4ERR)
1N/A espi->intr_cnt.DIP4_err++;
1N/A if (status & F_RXDROP)
1N/A espi->intr_cnt.rx_drops++;
1N/A if (status & F_TXDROP)
1N/A espi->intr_cnt.tx_drops++;
1N/A if (status & F_RXOVERFLOW)
1N/A espi->intr_cnt.rx_ovflw++;
1N/A if (status & F_RAMPARITYERR)
1N/A espi->intr_cnt.parity_err++;
1N/A if (status & F_DIP2PARITYERR) {
1N/A espi->intr_cnt.DIP2_parity_err++;
1N/A (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
1N/A }
1N/A
1N/A /*
1N/A * For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
1N/A * write the status as is.
1N/A */
1N/A if (status && t1_is_T1B(espi->adapter))
1N/A status = 1;
1N/A t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, status);
1N/A return 0;
1N/A}
1N/A
1N/Aconst struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
1N/A{
1N/A return &espi->intr_cnt;
1N/A}
1N/A
1N/Astatic void espi_setup_for_pm3393(adapter_t *adapter)
1N/A{
1N/A u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
1N/A t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
1N/A t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
1N/A t1_write_reg_4(adapter, A_PORT_CONFIG,
1N/A V_RX_NPORTS(1) | V_TX_NPORTS(1));
1N/A}
1N/A
1N/Astatic void espi_setup_for_vsc7321(adapter_t *adapter)
1N/A{
1N/A#ifdef CONFIG_CHELSIO_T1_COUGAR
1N/A u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
1N/A t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
1N/A t1_write_reg_4(adapter, A_PORT_CONFIG,
1N/A V_RX_NPORTS(1) | V_TX_NPORTS(1));
1N/A#else
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f401f4);
1N/A t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, 0xa00);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x1ff);
1N/A t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
1N/A t1_write_reg_4(adapter, A_PORT_CONFIG,
1N/A V_RX_NPORTS(4) | V_TX_NPORTS(4));
1N/A#endif
1N/A t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
1N/A}
1N/A
1N/A/*
1N/A * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug.
1N/A */
1N/Astatic void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
1N/A{
1N/A t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
1N/A if (nports == 4) {
1N/A if (is_T2(adapter)) {
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
1N/A 0xf00);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
1N/A 0x3c0);
1N/A } else {
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
1N/A 0x7ff);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
1N/A 0x1ff);
1N/A }
1N/A } else {
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
1N/A 0x1fff);
1N/A t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
1N/A 0x7ff);
1N/A }
1N/A t1_write_reg_4(adapter, A_PORT_CONFIG,
1N/A V_RX_NPORTS(nports) | V_TX_NPORTS(nports));
1N/A}
1N/A
1N/Aint t1_espi_init(struct peespi *espi, int mac_type, int nports)
1N/A{
1N/A u32 status_enable_extra = 0;
1N/A adapter_t *adapter = espi->adapter;
1N/A
1N/A /* Disable ESPI training. MACs that can handle it enable it below. */
1N/A t1_write_reg_4(adapter, A_ESPI_TRAIN, 0);
1N/A
1N/A if (is_T2(adapter)) {
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
1N/A V_OUT_OF_SYNC_COUNT(4) |
1N/A V_DIP2_PARITY_ERR_THRES(3) | V_DIP4_THRES(1));
1N/A t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2,
1N/A nports == 4 ? 0x200040 : 0x1000080);
1N/A } else
1N/A t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2, 0x800100);
1N/A
1N/A if (mac_type == CHBT_MAC_PM3393)
1N/A espi_setup_for_pm3393(adapter);
1N/A else if (mac_type == CHBT_MAC_VSC7321)
1N/A espi_setup_for_vsc7321(adapter);
1N/A else if (mac_type == CHBT_MAC_IXF1010) {
1N/A status_enable_extra = F_INTEL1010MODE;
1N/A espi_setup_for_ixf1010(adapter, nports);
1N/A } else
1N/A return -1;
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_FIFO_STATUS_ENABLE,
1N/A status_enable_extra | F_RXSTATUSENABLE);
1N/A
1N/A if (is_T2(adapter)) {
1N/A (void) tricn_init(adapter);
1N/A /*
1N/A * Always position the control at the 1st port egress IN
1N/A * (sop,eop) counter to reduce PIOs for T/N210 workaround.
1N/A */
1N/A espi->misc_ctrl = t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL);
1N/A espi->misc_ctrl &= ~MON_MASK;
1N/A espi->misc_ctrl |= F_MONITORED_DIRECTION;
1N/A if (adapter->params.nports == 1)
1N/A espi->misc_ctrl |= F_MONITORED_INTERFACE;
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
1N/A SPIN_LOCK_INIT(espi->lock);
1N/A }
1N/A
1N/A return 0;
1N/A}
1N/A
1N/Avoid t1_espi_destroy(struct peespi *espi)
1N/A{
1N/A if (is_T2(espi->adapter)) {
1N/A SPIN_LOCK_DESTROY(espi->lock);
1N/A }
1N/A t1_os_free((void *)espi, sizeof(*espi));
1N/A}
1N/A
1N/Astruct peespi *t1_espi_create(adapter_t *adapter)
1N/A{
1N/A struct peespi *espi = t1_os_malloc_wait_zero(sizeof(*espi));
1N/A
1N/A if (espi)
1N/A espi->adapter = adapter;
1N/A return espi;
1N/A}
1N/A
1N/Avoid t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
1N/A{
1N/A struct peespi *espi = adapter->espi;
1N/A
1N/A if (!is_T2(adapter))
1N/A return;
1N/A SPIN_LOCK(espi->lock);
1N/A espi->misc_ctrl = (val & ~MON_MASK) |
1N/A (espi->misc_ctrl & MON_MASK);
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
1N/A SPIN_UNLOCK(espi->lock);
1N/A}
1N/A
1N/Au32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
1N/A{
1N/A struct peespi *espi = adapter->espi;
1N/A u32 sel;
1N/A
1N/A if (!is_T2(adapter)) return 0;
1N/A sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
1N/A if (!wait) {
1N/A if (!SPIN_TRYLOCK(espi->lock))
1N/A return 0;
1N/A }
1N/A else
1N/A SPIN_LOCK(espi->lock);
1N/A if ((sel != (espi->misc_ctrl & MON_MASK))) {
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
1N/A ((espi->misc_ctrl & ~MON_MASK) | sel));
1N/A sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
1N/A espi->misc_ctrl);
1N/A }
1N/A else
1N/A sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
1N/A SPIN_UNLOCK(espi->lock);
1N/A return sel;
1N/A}
1N/A
1N/A/*
1N/A * This function is for T204 only.
1N/A * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in
1N/A * one shot, since there is no per port counter on the out side.
1N/A */
1N/Aint
1N/At1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
1N/A{
1N/A struct peespi *espi = adapter->espi;
1N/A u8 i, nport = (u8)adapter->params.nports;
1N/A
1N/A if (!wait) {
1N/A if (!SPIN_TRYLOCK(espi->lock))
1N/A return -1;
1N/A } else
1N/A SPIN_LOCK(espi->lock);
1N/A if ((espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION ) {
1N/A espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) |
1N/A F_MONITORED_DIRECTION;
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
1N/A }
1N/A for (i = 0 ; i < nport; i++, valp++) {
1N/A if (i) {
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
1N/A (espi->misc_ctrl | V_MONITORED_PORT_NUM(i)));
1N/A }
1N/A *valp = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
1N/A }
1N/A
1N/A t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
1N/A
1N/A SPIN_UNLOCK(espi->lock);
1N/A return 0;
1N/A}
1N/A