d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 //1= link up;0= link down
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 //1= full-duplex; 0= half-duplex
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 //1 = Indicates that the LP and the LD supports
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 // the BAM function for Clause 37 AN. This bit is
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // asserted when both the LD and the LP have
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // successfully exchanged BAM73 NPs and, therefore,
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // determined that a switch over to CL37 AN will follow
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 //bits [13:8]
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 //1= Fiber mode (1000X); 0= SGMII mode
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 //1= Ten Bit Interface; 0= GMII interface
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 //1= full-duplex; 0= half-duplex
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 //message page ID for over 1G next pages
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi// #define MDIO_OVER_1G_UP1_10G 0x0008 - yaronw
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi// #define MDIO_OVER_1G_UP1_10GH 0x0010 - yaronw
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 //force teton_mode override
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 //force teton_mode override value
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 //Clause73 BAM73 AN enable
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 //BAM73 Station Manager enable
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 //Enables STA to send BAM73 Next Pagess immediately after Base Page; otherwise send BAM73 NPs following software NPs
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 // Address Expansion Register
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 //The 2 bits are split
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 //0=half duplex
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 //status: 0=link fail; 1=link pass
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 //supports additional pages using NP function
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 //1=LP is NP able; 0= not able
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 //1=LP has received link code word
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi //#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_SYMMETRIC 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi //#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_ASYMMETRIC 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // When the link partner is in SGMII mode (bit 0 = 1), then
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // bit 15 = link, bit 12 = duplex, bits 11:10 = speed, bit 14 = acknowledge.
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi // The other bits are reserved and should be zero
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 //1=SGMII mode; 0=fiber mode
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi// Optical Ext PHY (8705/6) registers
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi// KR (8072) Registers
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020 //bit5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400 //bit10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800 //bit11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00 //bit10+bit11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00 //bit10+bit11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi// SFX7101 Registers
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //PHY_REG_H