d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchibit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
d14abf155341d55053c76eeec58b787a456b753bRobert MustacchiTheotherbitsarereservedandshouldbezero*/
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM84823 only */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* These pins configure the BCM84823 interface to MAC after reset. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* These pins configure the BCM84823 interface to Line after reset. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi /* When this pin is active high during reset, 10GBASE-T core is power
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi * down, When it is active low the 10GBASE-T is power up
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* BCM84833 only */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* These are mailbox register set used by 84833. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Mailbox command set used by 84833. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Mailbox status set used by 84833. */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Warpcore clause 45 addressing */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)