577xx_int_offsets.h revision d14abf155341d55053c76eeec58b787a456b753b
/*
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* If applicable, add the following below this CDDL HEADER, with the
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*
* Copyright 2014 QLogic Corporation
* The contents of this file are subject to the terms of the
* QLogic End User License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the License at
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*/
#ifndef __577XX_INT_OFFSETS__
#define __577XX_INT_OFFSETS__
/* Base physical address of slow path ring */
/* Producer of slow path ring. An update of this field triggers a slow path operation on the device */
/* Location of slow path ring data. Should be zeroed in function close process */
/* Base physical address of slow path ring (VFs) */
/* Producer of slow path ring. An update of this field triggers a slow path operation on the device (VFs) */
/* Location of slow path ring data. Should be zeroed in function close process (VFs) */
#define XSTORM_JUMBO_SUPPORT_OFFSET(pfId) (IRO[37].base + (((pfId)>>1) * IRO[37].m1) + (((pfId)&1) * IRO[37].m2))
/* TCP real time clock parameters */
/* Resolution of TCP real time clock */
/* Description Storms FW version number, written in Xstorm RAM upon init */
/* Offload licensing values */
/* Congestion management variables per port */
/* Rate shaping variables, per VNIC */
/* Fairness variables, per VNIC */
/* Offset of per-queue statistics in Xstorm. Need to be zeroes before clients which use this statistics queue are loaded. */
/* Function enable bit for Xstorm. Need to be set before a new function (PF or VF) is loaded. */
/* Maps between VF IDs and their parent PF */
/* When set, all slow path commands for this function are recorded in Storm�s assert memory (debug feature). */
/* Xstorm assert list location in RAM */
#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[50].base + ((assertListEntry) * IRO[50].m1))
/* Xstorm assert list index (producer) location in RAM */
/* Internal statistics of error handlers in Everets2 */
/* VF-accessible queue zone in Xstorm in Everest2 */
/* VF-accessible VF zone in Xstorm in Everest2 */
/* TCP real time clock parameters */
/* Tstorm assert list location in RAM */
#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[101].base + ((assertListEntry) * IRO[101].m1))
/* Tstorm assert list index (producer) location in RAM */
/* Tstorm Measure PCI Latency Control location in RAM */
/* Tstorm Measure PCI Latency Data location in RAM */
/* Description Function enable bit for Tstorm. Need to be set before a new function (PF or VF) is loaded. */
/* Maps between VF IDs and their parent PF */
/* When set, all slow path commands for this function are recorded in Storm�s assert memory (debug feature). */
/* Offset of per-queue statistics in Tstorm. Need to be zeroes before clients which use this statistics queue are loaded. */
#define TSTORM_PER_QUEUE_STATS_OFFSET(tStatQueueId) (IRO[110].base + ((tStatQueueId) * IRO[110].m1))
/* SAFC workaround handler enable, needed in Everest1h A0 only. */
/* SAFC workaround handler timeout, needed in Everest1h A0 only. */
/* Internal statistics of error handlers in Everets2 */
/* VF-accessible queue zone in Tstorm in Everest2 */
/* VF-accessible VF zone in Tstorm in Everest2 */
/* Status blocks location in Cstorm RAM */
/* Status blocks configuration location in Cstorm RAM */
/* Status blocks state configuration location in Cstorm RAM */
/* Status blocks timeout per index in Cstorm RAM */
#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId,hcIndex) (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
/* Status blocks flags per index in Cstorm RAM */
#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId,hcIndex) (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
/* Block of status block synchronization lines in Cstorm RAM */
/* Status block synchronization lines in Cstorm RAM (Everest2) */
#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex,sbId) (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) * IRO[142].m2) + ((sbId) * IRO[142].m3))
/* Status block synchronization lines in Cstorm RAM (Everest1/1h) */
#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex,sbId) (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
/* Dynamic host coalescing counter in synchronization lines */
#define CSTORM_HC_SYNC_LINE_DHC_OFFSET(sbSyncLines,sbId) (IRO[144].base + ((sbSyncLines) * IRO[144].m1) + ((sbId) * IRO[144].m2))
/* Slow path status blocks location in Cstorm RAM. */
/* Slow path status blocks configuration location in Cstorm RAM. */
/* Slow path status blocks state configuration location in Cstorm RAM. */
/* Block of slow path status blocks synchronization lines in Cstorm RAM. */
/* Slow path status blocks synchronization line in Cstorm RAM. */
#define CSTORM_SP_HC_SYNC_LINE_INDEX_OFFSET(hcSpIndex,pfId) (IRO[149].base + ((hcSpIndex) * IRO[149].m1) + ((pfId) * IRO[149].m2))
/* Configuration of dynamic host coalescing algorithm. */
/* Cstorm assert list location in RAM */
#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[151].base + ((assertListEntry) * IRO[151].m1))
/* Cstorm assert list index (producer) location in RAM */
/* Function enable bit for Cstorm. Need to be set before a new function (PF or VF) is loaded. */
/* Maps between VF IDs and their parent PF */
/* Configuration of dynamic host coalescing algorithm. */
/* Dynamic HC driver counter, written on fast path */
#define CSTORM_BYTE_COUNTER_OFFSET(sbId,dhcIndex) (IRO[156].base + ((sbId) * IRO[156].m1) + ((dhcIndex) * IRO[156].m2))
/* Event ring configuration location on Cstorm RAM */
#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * IRO[157].m2))
/* Event ring producer location on Cstorm RAM */
#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * IRO[158].m2))
/* Valid bit of VF-PF channel, used by PF driver to enable the communication channel. */
/* IGU mode to use in Everest2 (use enum igu_mode) */
/* Internal statistics of error handlers in Everets2 */
/* Driver polls this offset after FLR final cleanup operation to see when the cleanup operation finished */
/* VF-accessible queue zone in Cstorm in Everest2 */
/* VF-accessible VF zone in Cstorm in Everest2 */
/* Ustorm assert list location in RAM */
#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[180].base + ((assertListEntry) * IRO[180].m1))
/* Ustorm assert list index (producer) location in RAM */
/* Function enable bit for Ustorm. Need to be set before a new function (PF or VF) is loaded. */
/* Maps between VF IDs and their parent PF */
/* When set, all slow path commands for this function are recorded in Storm�s assert memory (debug feature). */
/* Offset of per-queue statistics in Ustorm. Need to be zeroes before clients which use this statistics queue are loaded. */
#define USTORM_PER_QUEUE_STATS_OFFSET(uStatQueueId) (IRO[185].base + ((uStatQueueId) * IRO[185].m1))
/* Valid physical address on host memory, used in Everest1 for PXP memory bug workaround */
/* Enable for pause on exhausted ring feature for Ethernet */
/* Enable for pause on exhausted ring feature for TOE */
/* Timeout for stopping sending pause commands from RX firmware, in order to avoid �constant pause� in case of driver not responding. */
/* Internal statistics of error handlers in Everets2 */
/* VF-accessible queue zone in Ustorm in Everest2 */
/* VF-accessible VF zone in Ustorm in Everest2 */
/* PF-related classification data, used in Everest1/1h */
/* PF-related filter bits, used in Everest1/1h */
/* PF-related approximate multicast bits, used in Everest1h */
#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) (IRO[207].base + ((pfId) * IRO[207].m1))
/* Set in order to accept packets which failed MF classification (for debug purpose) */
/* Set in order to accept packets which failed MF classification (for debug purpose) */
#define TSTORM_ACCEPT_CLASSIFY_FAIL_E2_ENABLE_OFFSET(portId) (IRO[209].base + ((portId) * IRO[209].m1))
/* Set the VNIC to accept packets which failed MF classification (for debug purpose) */
#define TSTORM_ACCEPT_CLASSIFY_FAIL_E2_VNIC_OFFSET(portId) (IRO[210].base + ((portId) * IRO[210].m1))
#define USTORM_CQE_PAGE_NEXT_OFFSET(portId,clientId) (IRO[211].base + ((portId) * IRO[211].m1) + ((clientId) * IRO[211].m2))
/* TPA aggregation data (should be zeroed by driver upon init as init tool has limitation of data unions) */
/* TPA aggregation timeout value */
/* Minimum byte count for a single packet in dynamic host coalescing counters */
/* RX rings producers, updated in fats path in Ustorm RAM (Everest1/1h) */
#define USTORM_RX_PRODS_E1X_OFFSET(portId,clientId) (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * IRO[215].m2))
/* RX rings producers, updated in fats path in Ustorm RAM (Everest2) */
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) (IRO[217].base + ((portId) * IRO[217].m1))
#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) (IRO[218].base + ((portId) * IRO[218].m1))
#define XSTORM_TCP_IPID_OFFSET(pfId) (IRO[219].base + (((pfId)>>1) * IRO[219].m1) + (((pfId)&1) * IRO[219].m2))
#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * IRO[220].m2))
#define XSTORM_TOE_LLC_SNAP_ENABLED_OFFSET(pfId) (IRO[227].base + (((pfId)>>1) * IRO[227].m1) + (((pfId)&1) * IRO[227].m2))
#define CSTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId) (IRO[233].base + ((rssId) * IRO[233].m1) + ((portId) * IRO[233].m2))
#define CSTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId) (IRO[234].base + ((rssId) * IRO[234].m1) + ((portId) * IRO[234].m2))
#define CSTORM_TOE_CQ_PROD_OFFSET(rssId,portId) (IRO[235].base + ((rssId) * IRO[235].m1) + ((portId) * IRO[235].m2))
#define CSTORM_TOE_CQ_CONS_OFFSET(rssId,portId) (IRO[236].base + ((rssId) * IRO[236].m1) + ((portId) * IRO[236].m2))
#define CSTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId) (IRO[237].base + ((rssId) * IRO[237].m1) + ((portId) * IRO[237].m2))
#define CSTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId) (IRO[238].base + ((rssId) * IRO[238].m1) + ((portId) * IRO[238].m2))
#define CSTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId) (IRO[239].base + ((rssId) * IRO[239].m1) + ((portId) * IRO[239].m2))
#define CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId) (IRO[240].base + ((rssId) * IRO[240].m1) + ((portId) * IRO[240].m2))
#define CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId) (IRO[241].base + ((rssId) * IRO[241].m1) + ((portId) * IRO[241].m2))
#define CSTORM_TOE_DYNAMIC_HC_PROD_OFFSET(rssId,portId) (IRO[242].base + ((rssId) * IRO[242].m1) + ((portId) * IRO[242].m2))
#define CSTORM_TOE_DYNAMIC_HC_CONS_OFFSET(rssId,portId) (IRO[243].base + ((rssId) * IRO[243].m1) + ((portId) * IRO[243].m2))
#define USTORM_GRQ_CACHE_BD_LO_OFFSET(rssId,portId,grqBdId) (IRO[244].base + ((rssId) * IRO[244].m1) + ((portId) * IRO[244].m2) + ((grqBdId) * IRO[244].m3))
#define USTORM_GRQ_CACHE_BD_HI_OFFSET(rssId,portId,grqBdId) (IRO[245].base + ((rssId) * IRO[245].m1) + ((portId) * IRO[245].m2) + ((grqBdId) * IRO[245].m3))
#define USTORM_TOE_GRQ_LOCAL_PROD_OFFSET(rssId,portId) (IRO[247].base + ((rssId) * IRO[247].m1) + ((portId) * IRO[247].m2))
#define USTORM_TOE_GRQ_LOCAL_CONS_OFFSET(rssId,portId) (IRO[248].base + ((rssId) * IRO[248].m1) + ((portId) * IRO[248].m2))
#define USTORM_TOE_GRQ_CONS_OFFSET(rssId,portId) (IRO[249].base + ((rssId) * IRO[249].m1) + ((portId) * IRO[249].m2))
#define USTORM_TOE_GRQ_PROD_OFFSET(rssId,portId) (IRO[250].base + ((rssId) * IRO[250].m1) + ((portId) * IRO[250].m2))
#define USTORM_TOE_GRQ_CONS_PTR_LO_OFFSET(rssId,portId) (IRO[251].base + ((rssId) * IRO[251].m1) + ((portId) * IRO[251].m2))
#define USTORM_TOE_GRQ_CONS_PTR_HI_OFFSET(rssId,portId) (IRO[252].base + ((rssId) * IRO[252].m1) + ((portId) * IRO[252].m2))
#define USTORM_TOE_GRQ_BUF_SIZE_OFFSET(rssId,portId) (IRO[253].base + ((rssId) * IRO[253].m1) + ((portId) * IRO[253].m2))
#define USTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId) (IRO[254].base + ((rssId) * IRO[254].m1) + ((portId) * IRO[254].m2))
#define USTORM_TOE_CQ_CONS_OFFSET(rssId,portId) (IRO[255].base + ((rssId) * IRO[255].m1) + ((portId) * IRO[255].m2))
#define USTORM_TOE_CQ_PROD_OFFSET(rssId,portId) (IRO[256].base + ((rssId) * IRO[256].m1) + ((portId) * IRO[256].m2))
#define USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId) (IRO[257].base + ((rssId) * IRO[257].m1) + ((portId) * IRO[257].m2))
#define USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId) (IRO[258].base + ((rssId) * IRO[258].m1) + ((portId) * IRO[258].m2))
#define USTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId) (IRO[259].base + ((rssId) * IRO[259].m1) + ((portId) * IRO[259].m2))
#define USTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId) (IRO[260].base + ((rssId) * IRO[260].m1) + ((portId) * IRO[260].m2))
#define USTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId) (IRO[261].base + ((rssId) * IRO[261].m1) + ((portId) * IRO[261].m2))
#define USTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId) (IRO[262].base + ((rssId) * IRO[262].m1) + ((portId) * IRO[262].m2))
#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) (IRO[271].base + ((pfId) * IRO[271].m1))
#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) (IRO[272].base + ((pfId) * IRO[272].m1))
#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) (IRO[273].base + ((pfId) * IRO[273].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) (IRO[280].base + ((pfId) * IRO[280].m1))
#define TSTORM_ISCSI_L2_ISCSI_OOO_RX_BDS_THRSHLD_OFFSET(pfId) (IRO[282].base + ((pfId) * IRO[282].m1))
#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId,iscsiEqId) (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId,iscsiEqId) (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId,iscsiEqId) (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId,iscsiEqId) (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId,iscsiEqId) (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId,iscsiEqId) (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId,iscsiEqId) (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
#define USTORM_CACHED_TCE_MNG_INFO_DWORD_ONE_OFFSET(cached_tbl_size) (IRO[338].base + ((cached_tbl_size) * IRO[338].m1))
#define USTORM_CACHED_TCE_MNG_INFO_DWORD_TWO_OFFSET(cached_tbl_size) (IRO[339].base + ((cached_tbl_size) * IRO[339].m1))
#define NUM_OF_INT_OFFSET_MACROS 385
#endif // __577XX_INT_OFFSETS__