lm_sb.c revision d14abf155341d55053c76eeec58b787a456b753b
/*******************************************************************************
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*
* Copyright 2014 QLogic Corporation
* The contents of this file are subject to the terms of the
* QLogic End User License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*
*
* Module Description:
* This file contains functions that handle IGU access and SB management
*
******************************************************************************/
#include "lm5710.h"
#include "577xx_int_offsets.h"
#include "bcmtype.h"
/* Reads IGU interrupt status register MSB / LSB */
static u32_t lm_read_isr32 (
{
do {
/* Read the 32 bit value from BAR */
/* Do one more iteration if we got the value for a legitimate "all ones" */
} while (value == 0xefffffff);
return res;
}
/* Reads IGU interrupt status register MSB / LSB */
static u64_t lm_read_isr64(
{
do {
/* Read the 32 bit value from BAR */
DbgMessage(pdev, FATAL, " ### lm_read_isr64 read address 0x%x value=0x%x 0x%x\n",addr,(u32_t)(value>>32),(u32_t)value);
/* Do one more iteration if we got the value for a legitimate "all ones" */
} while (value == 0xefffffffffffffffULL);
return res;
}
{
u64_t intr_status = 0;
return intr_status;
}
{
}
{
if (INTR_BLK_REQUIRE_CMD_CTRL(pdev)) {
/* This is IGU GRC Access... need to write ctrl and then read data */
}
/* if above, need to read 64 bits from IGU...and take care of all-ones */
return intr_status;
}
{
if (INTR_BLK_REQUIRE_CMD_CTRL(pdev)) {
/* This is IGU GRC Access... need to write ctrl and then read data */
}
/* if above, need to read 64 bits from IGU...and take care of all-ones */
return intr_status;
} /* lm_get_interrupt_status */
{
return LM_STATUS_SUCCESS;
}
{
{
if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_TOE_RX_CQ_CONS, is_enable)) != LM_STATUS_SUCCESS)
break;
if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_TOE_TX_CQ_CONS, is_enable)) != LM_STATUS_SUCCESS)
break;
if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_RX_CQ_CONS, is_enable)) != LM_STATUS_SUCCESS)
break;
if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_TX_CQ_CONS_COS0, is_enable)) != LM_STATUS_SUCCESS)
break;
if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_TX_CQ_CONS_COS1, is_enable)) != LM_STATUS_SUCCESS)
break;
if ((lm_status = lm_set_hc_flag(pdev, sb_id, HC_INDEX_ETH_TX_CQ_CONS_COS2, is_enable)) != LM_STATUS_SUCCESS)
break;
}
}
return lm_status;
}
{
}
{
}
{
}
{
}
{
DbgMessage(pdev, FATAL, "IGU test mode: returned %d fp-messages\n", pdev->hw_info.intr_blk_info.igu_info.igu_test_sb_cnt + pdev->hw_info.intr_blk_info.igu_info.igu_sb_cnt);
return (pdev->hw_info.intr_blk_info.igu_info.igu_test_sb_cnt + pdev->hw_info.intr_blk_info.igu_info.igu_sb_cnt);
}
} else {
}
}
{
return 1;
} else {
return 0;
}
}
{
return TRUE;
} else {
return FALSE;
}
}
{
struct hc_index_data * hc_index_entry;
if (CHIP_IS_E1x(pdev)) {
hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.index_data + idx;
} else {
hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.index_data + idx;
}
if (is_enable) {
}
} else {
}
}
}
if (notify_fw) {
if (CHIP_IS_E1x(pdev)) {
+ sizeof(struct hc_index_data)*idx
} else {
+ sizeof(struct hc_index_data)*idx
}
} else {
}
return lm_status;
}
{
u16_t atomic_index = 0;
*activity_flg = 0;
DbgBreakIf(!pdev);
//It's a default status block
{
(*activity_flg) |= LM_SP_ACTIVE;
}
{
(*activity_flg) |= LM_DEF_ATTN_ACTIVE;
}
}
void lm_update_fp_hc_indices(lm_device_t *pdev, u8_t igu_sb_id, u32_t *activity_flg, u8_t *drv_rss_id)
{
u16_t atomic_index = 0;
*activity_flg = 0;
{
}
}
{
if ((pdev->params.ndsb_type == LM_SINGLE_SM) || (pdev->params.ndsb_type == LM_DOUBLE_SM_SINGLE_IGU)) {
}
}
}
/* Fixme - doesn't have to be... */
*drv_rss_id = drv_sb_id;
}
{
{
return FALSE;
}
//it is legit that only a subgroup of the storms may change between our local copy.
//at least one storm index change implies that we have work to do on this sb
{
}
{
}
return result;
}
{
u16_t atomic_index = 0;
u8_t drv_rss_id = 0;
/* One Segment Per u/c */
} else {
//DbgMessage(pdev, FATAL, "Ustorm drv_sb_id=%d\n", drv_sb_id);
} else {
//DbgMessage(pdev, FATAL, "Cstorm drv_sb_id=%d\n", drv_sb_id);
}
}
}
//Check for Rx completions
{
//DbgMessage(pdev, FATAL, "RX_completion=%d\n", drv_rss_id);
}
#ifdef INCLUDE_L4_SUPPORT
//Check for L4 Rx completions
{
}
#endif
}
if (IGU_U_NDSB_OFFSET(pdev)) {
}
}
//Check for Tx completions
{
//DbgMessage(pdev, FATAL, "TX_completion=%d\n", drv_rss_id);
}
#ifdef INCLUDE_L4_SUPPORT
//Check for L4 Tx completions
{
}
#endif
}
*rx_rss_id = drv_rss_id;
*tx_rss_id = drv_rss_id;
return flags;
}
{
}
{
}
{
}
{
}
{
#if 0
DbgBreakIf(!pdev);
//print info of all non-default status blocks
{
DbgBreakIf(!rss_sb);
DbgBreakIf(*(LM_TXQ(pdev, index).hw_con_idx_ptr) != rss_sb->c_status_block.index_values[HC_INDEX_C_ETH_TX_CQ_CONS]);
DbgMessage(pdev, INFORMi, "rss sb #%d: u_new_cons:%d, c_new_cons:%d, c_status idx:%d, c_sbID:%d, u_status idx:%d, u_sbID:%d\n",
}
//print info of the default status block
pdev->vars.gen_sp_status_block.hc_sp_status_blk->sp_sb.running_index, pdev->vars.gen_sp_status_block.sb_data.igu_sb_id);
#endif
}
/**
* This function sets all the status-block ack values back to
* zero. Must be called BEFORE initializing the igu + before
* initializing status-blocks.
*
* @param pdev
*/
{
//init attn state
}
{
//give the IGU the status block number(ID) of attention bits section.
DbgBreakIf(!pdev);
//write to IGU the physical address where the attention bits lie
}
static void init_igu_attn_status_block(
struct _lm_device_t *pdev,
{
//write to IGU the physical address where the attention bits lie
DbgMessage(pdev, INFORMi, "init_attn_igu_status_block: host_sb_addr_low:0x%x; host_sb_addr_low:0x%x\n",
}
{
} else {
}
}
{
u8_t i;
DbgBreakIf(!pdev);
} else {
}
/* CQ#46240: Disable the function in the status-block data before nullifying sync-line + status-block */
REG_WR_DMAE_LEN_ZERO(pdev, CSEM_REG_FAST_MEMORY + CSTORM_SP_SYNC_BLOCK_OFFSET(func), CSTORM_SP_SYNC_BLOCK_SIZE/4);
REG_WR_DMAE_LEN_ZERO(pdev, CSEM_REG_FAST_MEMORY + CSTORM_SP_STATUS_BLOCK_OFFSET(func), CSTORM_SP_STATUS_BLOCK_SIZE/4);
for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32_t); i++) {
LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + i*sizeof(u32_t), *((u32_t*)&pdev->vars.gen_sp_status_block.sb_data + i), BAR_CSTRORM_INTMEM);
}
}
/* Initalize the whole status blocks per port - overall: 1 defalt sb, 16 non-default sbs
*
* Parameters:
* pdev - the LM device which holds the sbs
* port - the port number
*/
{
DbgBreakIf(!pdev);
//Read routing configuration for attn signal output of groups. Currently, only group 0,1,2 are wired.
{
//group index
REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0) + group_idx*16);
REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0) + group_idx*16);
REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0) + group_idx*16);
REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0) + group_idx*16);
/* enable5 is separate from the rest of the registers, and therefore the address skip is 4 and not 16 between the different groups */
REG_RD(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0) + group_idx*4);
} else {
}
DbgMessage(pdev, INFORMi, "lm_handle_deassertion_processing: group %d mask1:0x%x, mask2:0x%x, mask3:0x%x, mask4:0x%x, mask5:0x%x\n",
}
// init the non-default status blocks
{
}
}
// init the default status block - composed of 5 parts per storm: Attention bits, Ustorm, Cstorm, Xstorm, Tstorm
//Init the attention bits part of the default status block
}
/* set interrupt coalesing parameters.
- these settings are derived from user configured interrupt coalesing mode and tx/rx interrupts rate (lm params).
- these settings are used for status blocks initialization */
{
u32_t i = 0;
for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
rx_coal_usec[i] = 0;
}
for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
tx_coal_usec[i] = 0;
}
{
case LM_INT_COAL_PERIODIC_SYNC: /* static periodic sync */
for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
DbgMessage(pdev, WARN, "##lm_set_int_coal_info: int_per_sec_rx[%d] = %d\n",i,pdev->params.int_per_sec_rx[i]);
{
}
if(rx_coal_usec[i] > 0x3ff)
{
}
}
for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
DbgMessage(pdev, WARN, "##lm_set_int_coal_info: int_per_sec_tx[%d] = %d\n",i,pdev->params.int_per_sec_tx[i]);
{
}
if(tx_coal_usec[i] > 0x3ff)
{
}
}
break;
case LM_INT_COAL_NONE: /* this is the default */
default:
break;
}
/* set hc period for c sb for all indices */
for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
}
/* set hc period for u sb for all indices */
for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
}
#if 0
/* set TOE HC to minimum possible for ustorm */
}
#endif
/* by default set hc period for x/t/c/u defualt sb to NONE.
(that was already implicitly done by memset 0 above) */
/* set dynamic hc params */
for (i = 0; i < HC_USTORM_SB_NUM_INDICES; i++) {
ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout0[i] = (u8_t)pdev->params.hc_timeout0[SM_RX_ID][i];
ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout1[i] = (u8_t)pdev->params.hc_timeout1[SM_RX_ID][i];
ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout2[i] = (u8_t)pdev->params.hc_timeout2[SM_RX_ID][i];
ic->eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout3[i] = (u8_t)pdev->params.hc_timeout3[SM_RX_ID][i];
}
for (i = 0; i < HC_CSTORM_SB_NUM_INDICES; i++) {
ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout0[i] = (u8_t)pdev->params.hc_timeout0[SM_TX_ID][i];
ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout1[i] = (u8_t)pdev->params.hc_timeout1[SM_TX_ID][i];
ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout2[i] = (u8_t)pdev->params.hc_timeout2[SM_TX_ID][i];
ic->eth_dynamic_hc_cfg.sm_config[SM_TX_ID].hc_timeout3[i] = (u8_t)pdev->params.hc_timeout3[SM_TX_ID][i];
}
}
void lm_setup_ndsb_index(struct _lm_device_t *pdev, u8_t sb_id, u8_t idx, u8_t sm_idx, u8_t timeout, u8_t dhc_enable)
{
struct hc_index_data * hc_index_entry;
if (CHIP_IS_E1x(pdev)) {
hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.index_data + idx;
} else {
hc_index_entry = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.index_data + idx;
}
if (timeout) {
}
if (dhc_enable) {
}
}
void lm_setup_ndsb_state_machine(struct _lm_device_t *pdev, u8_t sb_id, u8_t sm_id, u8_t igu_sb_id, u8_t igu_seg_id)
{
struct hc_status_block_sm * hc_state_machine;
if (CHIP_IS_E1x(pdev)) {
hc_state_machine = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.state_machine + sm_id;
} else {
hc_state_machine = pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.state_machine + sm_id;
}
}
void lm_int_hc_ack_sb(lm_device_t *pdev, u8_t rss_id, u8_t storm_id, u16_t sb_index, u8_t int_op, u8_t is_update_idx)
{
struct igu_ack_register hc_data;
//this is the result which should be communicated to the driver!
//don't forget this
hc_data.sb_id_and_flags = 0;
DbgMessage(pdev, INFORMi, "lm_int_ack_sb() inside! rss_id:%d, sb_index:%d, func_num:%d is_update:%d\n", rss_id, sb_index, FUNC_ID(pdev), is_update_idx);
DbgMessage(pdev, INFORMi, "lm_int_ack_sb() inside! data:0x%x; status_block_index:%d\n", hc_data.sb_id_and_flags, hc_data.status_block_index);
// interrupt ack
}
void lm_int_igu_ack_sb(lm_device_t *pdev, u8_t igu_sb_id, u8_t segment_access, u16_t sb_index, u8_t int_op, u8_t is_update_idx)
{
struct igu_regular cmd_data;
struct igu_ctrl_reg cmd_ctrl;
//DbgMessage(pdev, FATAL, "int-igu-ack segment_access=%d\n", segment_access);
/*
* We may get here with IGU disabled. In that case, no IGU access is permitted.
*/
{
return;
}
((sb_index << IGU_REGULAR_SB_INDEX_SHIFT) |
} else {
}
} else {
u8_t igu_func_id = 0;
/* GRC ACCESS: */
/* Write the Data, then the control */
/* [18:12] - FID (if VF - [18] = 0; [17:12] = VF number; if PF - [18] = 1; [17:14] = 0; [13:12] = PF number) */
((cmd_addr << IGU_CTRL_REG_ADDRESS_SHIFT) |
}
}
{
struct igu_regular cmd_data = {0};
struct igu_ctrl_reg cmd_ctrl = {0};
#ifdef _VBD_CMD_
return;
#endif
/* Not supported in backward compatible mode! */
{
return;
}
/* Cleanup can be done only via GRC access using the producer update command */
/* wait for clean up to finish */
{
}
{
DbgMessage(pdev, FATAL, "Unable to finish IGU cleanup - set: igu_sb_id %d offset %d bit %d (cnt %d)\n",
}
/* Now we clear the cleanup-bit... same command without cleanup_set... */
/* wait for clean up to finish */
{
}
{
DbgMessage(pdev, FATAL, "Unable to finish IGU cleanup - clear: igu_sb_id %d offset %d bit %d (cnt %d)\n",
}
}
{
lm_int_hc_ack_sb(pdev, DEF_STATUS_BLOCK_IGU_INDEX, HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_DISABLE, 0); //DEF_STATUS_BLOCK_INDEX
} else {
lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_DISABLE, 0);
} else {
lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), IGU_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_DISABLE, 1);
}
}
}
/* Assumptions: Called when acking a status-block and enabling interrupts */
{
lm_int_hc_ack_sb(pdev, DEF_STATUS_BLOCK_IGU_INDEX, HC_SEG_ACCESS_ATTN, DEF_SB_INDEX_OF_ATTN(pdev), IGU_INT_NOP, 1); //DEF_STATUS_BLOCK_INDEX
lm_int_hc_ack_sb(pdev, DEF_STATUS_BLOCK_IGU_INDEX, HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_ENABLE, 1); //DEF_STATUS_BLOCK_INDEX
} else {
lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), HC_SEG_ACCESS_ATTN, DEF_SB_INDEX_OF_ATTN(pdev), IGU_INT_NOP, 1);
lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), HC_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_ENABLE, 1);
} else {
lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), IGU_SEG_ACCESS_ATTN, DEF_SB_INDEX_OF_ATTN(pdev), IGU_INT_NOP, 1);
lm_int_igu_ack_sb(pdev, IGU_DSB_ID(pdev), IGU_SEG_ACCESS_DEF, DEF_SB_INDEX(pdev), IGU_INT_ENABLE, 1);
}
}
}
{
} else {
} else {
//DbgMessage(pdev, WARN, "********lm_int_ack_sb_disable() during DPC\n");
// REG_WR(PFDEV(pdev), IGU_REG_ECO_RESERVED, 8);
// DbgBreak();
}
{
}
else
{
}
}
}
}
{
} else {
lm_int_igu_ack_sb(pdev, rss_id + IGU_BASE_NDSB(pdev) , HC_SEG_ACCESS_NORM, SB_RX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
} else {
{
lm_int_igu_ack_sb(pdev, rss_id + IGU_BASE_NDSB(pdev), IGU_SEG_ACCESS_NORM, SB_RX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
}
else
{
lm_int_igu_ack_sb(pdev, IGU_VF_NDSB(pdev,rss_id), IGU_SEG_ACCESS_NORM, SB_RX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
}
} else {
lm_int_igu_ack_sb(pdev, rss_id + IGU_BASE_NDSB(pdev), IGU_SEG_ACCESS_NORM, SB_TX_INDEX(pdev,rss_id), IGU_INT_ENABLE, 1);
}
}
}
}
{
DbgBreakIf(!pdev);
val = 0x1000;
case LM_INT_MODE_INTA:
/* we trust that if we're in inta... the os will take care of the configuration space...and therefore
* that will determine whether we are in inta or msix and not this configuration, we can't take down msix
* due to a hw bug */
if (CHIP_IS_E1(pdev))
{
}
break;
case LM_INT_MODE_SIMD:
break;
case LM_INT_MODE_MIMD:
break;
default:
DbgBreakMsg("Wrong Interrupt Mode\n");
return;
}
if (CHIP_IS_E1(pdev))
{
}
if(!CHIP_IS_E1(pdev))
{
if(IS_MULTI_VNIC(pdev))
{
/* in mf mode:
* - Set only VNIC bit out of the "per vnic group attentions" (bits[4-7]) */
/* Connect to PMF to NIG attention bit 8 */
val |= 0x1100;
}
} else
{
val = 0xffff;
}
}
}
{
return LM_STATUS_INVALID_PARAMETER;
}
#ifdef VF_INVOLVED
if (lm_status != LM_STATUS_SUCCESS) {
return lm_status;
}
return lm_status;
}
#endif
case LM_INT_MODE_INTA:
break;
case LM_INT_MODE_SIMD:
break;
case LM_INT_MODE_MIMD:
break;
default:
DbgBreakMsg("Wrong Interrupt Mode\n");
return LM_STATUS_FAILURE;
}
if(!CHIP_IS_E1(pdev))
{
if(IS_MULTI_VNIC(pdev))
{
/* in mf mode:
* - Do not set the link attention (bit 11) (will be set by MCP for the PMF)
* - Set only VNIC bit out of the "per vnic group attentions" (bits[4-7]) */
/* Connect to PMF to NIG attention bit 8 */
val |= 0x1100;
}
} else
{
val = 0xffff;
}
if (CHIP_IS_E3(pdev)) {
}
}
return LM_STATUS_SUCCESS;
}
{
} else {
}
}
{
DbgBreakIf(!pdev);
/* disable both bits, for INTA, MSI and MSI-X. */
if (CHIP_IS_E1(pdev))
{
/* E1 Errate: can't ever take msix bit down */
}
}
{
DbgBreakIf(!pdev);
#ifdef VF_INVOLVED
return;
}
#endif
/* disable both bits, for INTA, MSI and MSI-X. */
}
{
} else {
}
}
{
u8_t igu_seg_id = 0;
DbgBreakIf(!pdev);
/* CQ#46240: Disable the function in the status-block data before nullifying sync-line + status-block */
/* nullify the status block */
LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
}
LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
}
/* Initialize cstorm_status_block_data structure */
if (CHIP_IS_E1x(pdev)) {
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.vf_valid = FALSE;
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data.common.p_func.vnic_id = VNIC_ID(pdev);
} else {
}
} else {
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
} else {
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.vf_id = ABS_VFID(pdev);
}
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.p_func.vnic_id = VNIC_ID(pdev);
} else {
}
pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data.common.dhc_qzone_id = dhc_qzone_id;
}
} else {
}
lm_setup_ndsb_state_machine(pdev, sb_id, SM_RX_ID, igu_sb_id + IGU_U_NDSB_OFFSET(pdev), igu_seg_id);
}
//init host coalescing params - supported dymanicHC indices
if (CHIP_IS_E1x(pdev)) {
} else {
}
if (index < HC_DHC_SB_NUM_INDICES) {
} else {
dhc_enable = FALSE;
}
switch (index) {
case HC_INDEX_TOE_RX_CQ_CONS:
case HC_INDEX_ETH_RX_CQ_CONS:
case HC_INDEX_FCOE_EQ_CONS:
} else {
}
break;
case HC_INDEX_TOE_TX_CQ_CONS:
} else {
}
} else {
}
} else {
}
break;
} else {
}
// TODO Shayh: HC_PARAMS_ETH_INDEX (DYNAMIC_HC_ETH_INDEX) Should be handeled better from registry
// (not as part of this submit) .
break;
case HC_INDEX_ISCSI_EQ_CONS:
} else {
}
// DYNAMIC_HC_ISCSI_INDEX
break;
default:
} else {
}
dhc_enable = FALSE;
break;
}
}
if (CHIP_IS_E1x(pdev)) {
*((u32_t*)(&pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e1x_sb_data) + index), BAR_CSTRORM_INTMEM);
}
} else {
*((u32_t*)(&pdev->vars.status_blocks_arr[sb_id].hc_status_block_data.e2_sb_data) + index), BAR_CSTRORM_INTMEM);
}
}
}
/**
* @description
* Get the HC_INDEX_ETH_TX_CQ_CONS_COSX index from chain.
* @param pdev
* @param chain
*
* @return STATIC u8_t
*/
{
switch(cos)
{
case 0:
break;
case 1:
break;
case 2:
break;
default:
DbgBreakMsg("Invalid cos");
break;
}
return sb_index_number;
}
#ifdef VF_INVOLVED
lm_status_t lm_pf_init_vf_non_def_sb(struct _lm_device_t *pdev, lm_vf_info_t *vf_info, u8_t sb_idx, u64 sb_addr)
{
u8_t igu_seg_id = 0;
DbgBreakIf(!pdev);
/* CQ#46240: Disable the function in the status-block data before nullifying sync-line + status-block */
/* nullify the status block */
LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
}
LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
}
} else {
DbgBreak();
}
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.host_sb_addr.lo = sb_phy_address.as_u32.low;
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.host_sb_addr.hi = sb_phy_address.as_u32.high;
/* Initialize cstorm_status_block_data structure */
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.pf_id = FUNC_ID(pdev);
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.vf_id = vf_info->abs_vf_id;
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.vf_valid = TRUE;
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.p_func.vnic_id = VNIC_ID(pdev);
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.same_igu_sb_1b = TRUE;
} else {
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.same_igu_sb_1b = FALSE;
}
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.dhc_qzone_id = dhc_qzone_id;
pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data.common.state = SB_ENABLED;
} else {
DbgBreak();
}
lm_setup_ndsb_state_machine(pdev, LM_SW_VF_SB_ID(vf_info,sb_idx), SM_RX_ID, igu_sb_id + IGU_U_NDSB_OFFSET(pdev), igu_seg_id);
}
//init host coalescing params - supported dymanicHC indices
if (CHIP_IS_E1x(pdev)) {
DbgBreak();
} else {
}
if (index < HC_DHC_SB_NUM_INDICES) {
} else {
dhc_enable = FALSE;
}
switch (index) {
case HC_INDEX_TOE_RX_CQ_CONS:
case HC_INDEX_ETH_RX_CQ_CONS:
case HC_INDEX_FCOE_EQ_CONS:
} else {
}
break;
case HC_INDEX_TOE_TX_CQ_CONS:
} else {
}
} else {
}
} else {
}
break;
} else {
}
// TODO Shayh: HC_PARAMS_ETH_INDEX (DYNAMIC_HC_ETH_INDEX) Should be handeled better from registry
// (not as part of this submit) .
break;
case HC_INDEX_ISCSI_EQ_CONS:
} else {
}
// DYNAMIC_HC_ISCSI_INDEX
break;
default:
} else {
}
dhc_enable = FALSE;
break;
}
}
if (!CHIP_IS_E1x(pdev)) {
*((u32_t*)(&pdev->vars.status_blocks_arr[LM_SW_VF_SB_ID(vf_info,sb_idx)].hc_status_block_data.e2_sb_data) + index), BAR_CSTRORM_INTMEM);
}
} else {
DbgBreak();
}
return lm_status;
}
#endif //VF_INVOLVED
{
DbgBreakIf(!pdev);
/* nullify the status block */
LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
}
LM_INTMEM_WRITE32(PFDEV(pdev), CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id) + 4*index, 0, BAR_CSTRORM_INTMEM);
}
}