ecore_init.h revision d14abf155341d55053c76eeec58b787a456b753b
#ifndef ECORE_INIT_H
#define ECORE_INIT_H
#include "init_defs.h"
#include "aeu_inputs.h"
#if defined(_B10KD_EXT)
#include "b10ext_redefs.h"
#include "b10ext.h"
#endif
/* Returns the index of start or end of a specific block stage in ops array*/
#define INITOP_SET 0 /* set the HW directly */
/****************************************************************************
* ILT management
****************************************************************************/
struct ilt_line {
void *page;
};
struct ilt_client_info {
#define ILT_CLIENT_SKIP_INIT 0x1
#define ILT_CLIENT_SKIP_MEM 0x2
};
struct ecore_ilt {
#define ILT_CLIENT_CDU 0
#define ILT_CLIENT_QM 1
#define ILT_CLIENT_SRC 2
#define ILT_CLIENT_TM 3
};
/****************************************************************************
* SRC configuration
****************************************************************************/
struct src_ent {
};
/****************************************************************************
* Parity configuration
****************************************************************************/
{ \
}
{ \
}
{ \
}
static const struct {
struct {
} reg_mask; /* Register mask (all valid bits) */
* (name + suffix)
*/
} ecore_blocks_parity_data[] = {
/* bit 19 masked */
/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
/* bit 5,18,20-31 */
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
/* bit 5 */
/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
* want to handle "system kill" flow at the moment.
*/
0x7ffffff),
0xffffffff),
{0xf, 0xf, 0xf, 0xf}, "UPB"},
{0xf, 0xf, 0xf, 0xf}, "XPB"},
0xffffffff),
0xffffffff),
0xffffffff),
0xffffffff),
};
/* [28] MCP Latched rom_parity
* [29] MCP Latched ump_rx_parity
* [30] MCP Latched ump_tx_parity
* [31] MCP Latched scpad_parity
*/
#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
/* Below registers control the MCP parity attention output. When
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
* enabled, when cleared - disabled.
*/
static const struct {
} mcp_attn_ctl_regs[] = {
};
{
int i;
for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {
if (enable)
else
}
}
{
if (CHIP_IS_E1(pdev))
else if (CHIP_IS_E1H(pdev))
else if (CHIP_IS_E2(pdev))
else /* CHIP_IS_E3 */
}
{
int i;
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
if (dis_mask) {
dis_mask);
"for %s to\t\t0x%x\n",
}
}
/* Disable MCP parity attentions */
}
/**
* Clear the parity error status registers.
*/
{
int i;
/* Clear SEM_FAST parities */
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
if (reg_mask) {
"Parity errors in %s: 0x%x\n",
}
}
}
/* Check if there were parity attentions in MCP */
if (reg_val & mcp_aeu_bits) {
reg_val & mcp_aeu_bits);
}
/* Clear parity attentions in MCP:
* [7] clears Latched rom_parity
* [8] clears Latched ump_rx_parity
* [9] clears Latched ump_tx_parity
* [10] clears Latched scpad_parity (both ports)
*/
}
{
int i;
for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {
if (reg_mask)
}
/* Enable MCP parity attentions */
}
#endif /* ECORE_INIT_H */