bge_mii.c revision dc3f9a75e59d7bf1277d035ab1a4875c720910f9
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include "bge_impl.h"
/*
* Bit test macros, returning boolean_t values
*/
/*
* ========== Copper (PHY) support ==========
*/
/*
* #defines:
* BGE_COPPER_WIRESPEED controls whether the Broadcom WireSpeed(tm)
* feature is enabled. We need to recheck whether this can be
* enabled; at one time it seemed to interact unpleasantly with the
* loopback modes.
*
* BGE_COPPER_IDLEOFF controls whether the (copper) PHY power is
* turned off when the PHY is idled i.e. during driver suspend().
* For now this is disabled because the chip doesn't seem to
* resume cleanly if the PHY power is turned off.
*/
#define BGE_COPPER_WIRESPEED B_TRUE
#define BGE_COPPER_IDLEOFF B_FALSE
/*
* The arrays below can be indexed by the MODE bits from the Auxiliary
*/
static const int16_t bge_copper_link_speed[] = {
0, /* MII_AUX_STATUS_MODE_NONE */
10, /* MII_AUX_STATUS_MODE_10_H */
10, /* MII_AUX_STATUS_MODE_10_F */
100, /* MII_AUX_STATUS_MODE_100_H */
0, /* MII_AUX_STATUS_MODE_100_4 */
100, /* MII_AUX_STATUS_MODE_100_F */
1000, /* MII_AUX_STATUS_MODE_1000_H */
1000 /* MII_AUX_STATUS_MODE_1000_F */
};
static const int8_t bge_copper_link_duplex[] = {
LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */
LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */
LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */
LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */
LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */
LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */
LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_1000_H */
LINK_DUPLEX_FULL /* MII_AUX_STATUS_MODE_1000_F */
};
static const int16_t bge_copper_link_speed_5906[] = {
0, /* MII_AUX_STATUS_MODE_NONE */
10, /* MII_AUX_STATUS_MODE_10_H */
10, /* MII_AUX_STATUS_MODE_10_F */
100, /* MII_AUX_STATUS_MODE_100_H */
0, /* MII_AUX_STATUS_MODE_100_4 */
100, /* MII_AUX_STATUS_MODE_100_F */
0, /* MII_AUX_STATUS_MODE_1000_H */
0 /* MII_AUX_STATUS_MODE_1000_F */
};
static const int8_t bge_copper_link_duplex_5906[] = {
LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */
LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */
LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */
LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */
LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */
LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */
LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_1000_H */
LINK_DUPLEX_UNKNOWN /* MII_AUX_STATUS_MODE_1000_F */
};
#if BGE_DEBUGGING
static void
{
int i;
for (i = 0; i < 32; ++i)
switch (i) {
default:
break;
case MII_STATUS:
regs[i] = mii_status;
break;
case MII_AUX_STATUS:
break;
case 0x0b: case 0x0c: case 0x0d: case 0x0e:
case 0x15: case 0x16: case 0x17:
case 0x1c:
case 0x1f:
/* reserved registers -- don't read these */
regs[i] = 0;
break;
}
for (i = 0; i < 32; i += 8)
BGE_DEBUG(("bge_phydump: "
"0x%04x %04x %04x %04x %04x %04x %04x %04x",
}
#endif /* BGE_DEBUGGING */
/*
* Basic low-level function to probe for a PHY
*
* Returns TRUE if the PHY responds with valid data, FALSE otherwise
*/
static boolean_t
{
if (nicsig == BGE_NIC_DATA_SIG) {
switch (niccfg & BGE_NIC_CFG_PHY_TYPE_MASK) {
default:
return (B_TRUE);
return (B_FALSE);
}
} else {
/*
* Read the MII_STATUS register twice, in
* order to clear any sticky bits (but they should
* have been cleared by the RESET, I think).
*/
/*
* Now check the value read; it should have at least one bit set
* (for the device capabilities) and at least one clear (one of
* the error bits). So if we see all 0s or all 1s, there's a
* problem. In particular, bge_mii_get16() returns all 1s if
* communications fails ...
*/
switch (miicfg) {
case 0x0000:
case 0xffff:
return (B_FALSE);
default :
return (B_TRUE);
}
}
}
/*
* Basic low-level function to reset the PHY.
* Doesn't incorporate any special-case workarounds.
*
* Returns TRUE on success, FALSE if the RESET bit doesn't clear
*/
static boolean_t
{
if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
drv_usecwait(40);
/* put PHY into ready state */
drv_usecwait(40);
}
/*
* Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
*/
drv_usecwait(5);
return (B_TRUE);
}
(void) bge_adj_volt_5906(bgep);
return (B_FALSE);
}
/*
* Basic low-level function to powerdown the PHY, if supported
* If powerdown support is compiled out, this function does nothing.
*/
static void
{
BGE_TRACE(("bge_phy_powerdown"));
#endif /* BGE_COPPER_IDLEOFF */
}
/*
* The following functions are based on sample code provided by
* Broadcom (20-June-2003), and implement workarounds said to be
* required on the early revisions of the BCM5703/4C.
*
* The registers and values used are mostly UNDOCUMENTED, and
* therefore don't have symbolic names ;-(
*
* Many of the comments are straight out of the Broadcom code:
* even where the code has been restructured, the original
* comments have been preserved in order to explain what these
* undocumented registers & values are all about ...
*/
static void
{
break;
}
/*
* PHY test data pattern:
*
* For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6)
* For 5705, each DFE TAP has 19-bits (low word 15, hi word 4)
* For simplicity, we check only 19-bits, so we don't have to
* distinguish which chip it is.
* the LO word contains 15 bits, make sure pattern data is < 0x7fff
* the HI word contains 6 bits, make sure pattern data is < 0x003f
*/
#define N_CHANNELS 4
#define N_TAPS 3
static struct {
{
},
{
},
{
},
{
}
};
/*
* Check whether the PHY has locked up after a RESET.
*
* Returns TRUE if it did, FALSE is it's OK ;-)
*/
static boolean_t
{
/*
* Check TAPs for all 4 channels, as soon as we see a lockup
* we'll stop checking.
*/
/* Select channel and set TAP index to 0 */
/* Freeze filter again just to be safe */
/*
* Write fixed pattern to the RAM, 3 TAPs for
*/
}
/*
* Active PHY's Macro operation to write DFE
* TAP from RAM, and wait for Macro to complete.
*/
/*
* Done with write phase, now begin read phase.
*/
/* Select channel and set TAP index to 0 */
/*
* Active PHY's Macro operation to load DFE
* TAP to RAM, and wait for Macro to complete
*/
/* Enable "pre-fetch" */
/*
* Read back the TAP values. 3 TAPs for each
*/
/*
* For DFE TAP, the HI word contains 6 bits,
* LO word contains 15 bits
*/
/*
* Check if what we wrote is what we read back.
* If failed, then the PHY is locked up, we need
* to do PHY reset again
*/
return (B_TRUE); /* wedged! */
return (B_TRUE); /* wedged! */
}
}
/*
* The PHY isn't locked up ;-)
*/
return (B_FALSE);
}
/*
* Special-case code to reset the PHY on the 5702/5703/5704C/5705/5782.
* Tries up to 5 times to recover from failure to reset or PHY lockup.
*
* Returns TRUE on success, FALSE if there's an unrecoverable problem
*/
static boolean_t
{
/* Issue a phy reset, and wait for reset to complete */
/* Assuming reset is successful first */
/*
* Now go check the DFE TAPs to see if locked up, but
* first, we need to set up PHY so we can read DFE
* TAPs.
*/
/*
* Disable Transmitter and Interrupt, while we play
* with the PHY registers, so the link partner won't
* see any strange data and the Driver won't see any
* interrupts.
*/
/* Setup Full-Duplex, 1000 mbps */
/* Set to Master mode */
/* Enable SM_DSP_CLOCK & 6dB */
/* Work-arounds */
/* More workarounds */
/* Blocks the PHY control access */
/* Test whether PHY locked up ;-( */
if (reset_success && !phy_locked)
break;
/*
* Some problem here ... log it & retry
*/
if (!reset_success)
if (phy_locked)
}
/* Remove block phy control */
/* Unfreeze DFE TAP filter for all channels */
/* Restore PHY back to operating state */
/* Restore 1000BASE-T Control Register */
/* Enable transmitter and interrupt */
(void) bge_adj_volt_5906(bgep);
if (!reset_success)
else if (phy_locked)
return (reset_success && !phy_locked);
}
static void
{
/* Tweak GMII timing */
}
/* Bit Error Rate reduction fix */
static void
{
}
/*
* End of Broadcom-derived workaround code *
*/
static int
{
default:
/*
* Shouldn't happen; it means we don't recognise this chip.
* It's probably a new one, so we'll try our best anyway ...
*/
case MHCR_CHIP_ASIC_REV_5703:
case MHCR_CHIP_ASIC_REV_5704:
case MHCR_CHIP_ASIC_REV_5705:
case MHCR_CHIP_ASIC_REV_5752:
case MHCR_CHIP_ASIC_REV_5714:
case MHCR_CHIP_ASIC_REV_5715:
break;
case MHCR_CHIP_ASIC_REV_5906:
case MHCR_CHIP_ASIC_REV_5700:
case MHCR_CHIP_ASIC_REV_5701:
case MHCR_CHIP_ASIC_REV_5723:
/*
* Just a plain reset; the "check" code breaks these chips
*/
if (!reset_ok)
break;
}
if (!reset_ok) {
return (DDI_FAILURE);
}
/*
* Step 5: disable WOL (not required after RESET)
*
* Step 6: refer to errata
*/
default:
break;
case MHCR_CHIP_REV_5704_A0:
break;
}
case MHCR_CHIP_ASIC_REV_5705:
break;
}
/* Set the GMII Fifo Elasticity to high latency */
/* Allow reception of extended length packets */
auxctrl |= 0x4000;
}
/*
* Step 7: read the MII_INTR_STATUS register twice,
* in order to clear any sticky bits (but they should
* have been cleared by the RESET, I think), and we're
* not using PHY interrupts anyway.
*
* Step 8: enable the PHY to interrupt on link status
* change (not required)
*
* Step 9: configure PHY LED Mode - not applicable?
*
* Step 10: read the MII_STATUS register twice, in
* order to clear any sticky bits (but they should
* have been cleared by the RESET, I think).
*/
/*
* Finally, shut down the PHY, if required
*/
if (powerdown)
return (DDI_SUCCESS);
}
/*
* Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities
* and advertisements with the required settings as specified by the various
* param_* variables that can be poked via the NDD interface.
*
* We always reset the PHY and reprogram *all* the relevant registers,
* not just those changed. This should cause the link to go down, and then
* back up again once the link is stable and autonegotiation (if enabled)
* is complete. We should get a link state change interrupt somewhere along
* the way ...
*
* NOTE: <genlock> must already be held by the caller
*/
static int
{
BGE_DEBUG(("bge_update_copper: autoneg %d "
"pause %d asym_pause %d "
"1000fdx %d 1000hdx %d "
"100fdx %d 100hdx %d "
"10fdx %d 10hdx %d ",
/*
* PHY settings are normally based on the param_* variables,
* but if any loopback mode is in effect, that takes precedence.
*
* BGE supports MAC-internal loopback, PHY-internal loopback,
* and External loopback at a variety of speeds (with a special
* cable). In all cases, autoneg is turned OFF, full-duplex
* is turned ON, and the speed/mastership is forced.
*/
switch (bgep->param_loop_mode) {
case BGE_LOOP_NONE:
default:
break;
case BGE_LOOP_EXTERNAL_1000:
case BGE_LOOP_EXTERNAL_100:
case BGE_LOOP_EXTERNAL_10:
case BGE_LOOP_INTERNAL_PHY:
case BGE_LOOP_INTERNAL_MAC:
switch (bgep->param_loop_mode) {
case BGE_LOOP_EXTERNAL_1000:
break;
case BGE_LOOP_EXTERNAL_100:
adv_100fdx = B_TRUE;
break;
case BGE_LOOP_EXTERNAL_10:
break;
case BGE_LOOP_INTERNAL_PHY:
break;
case BGE_LOOP_INTERNAL_MAC:
break;
}
}
BGE_DEBUG(("bge_update_copper: autoneg %d "
"pause %d asym_pause %d "
"1000fdx %d 1000hdx %d "
"100fdx %d 100hdx %d "
"10fdx %d 10hdx %d ",
/*
* We should have at least one technology capability set;
* if not, we select a default of 1000Mb/s full-duplex
*/
/*
* Now transform the adv_* variables into the proper settings
* of the PHY registers ...
*
* If autonegotiation is (now) enabled, we want to trigger
* a new autonegotiation cycle once the PHY has been
* programmed with the capabilities to be advertised.
*/
if (adv_autoneg)
if (adv_1000fdx)
else if (adv_1000hdx)
else if (adv_100fdx)
else if (adv_100hdx)
else if (adv_10fdx)
else if (adv_10hdx)
control |= 0;
else
if (adv_1000fdx)
if (adv_1000hdx)
if (adv_100fdx)
if (adv_100hdx)
if (adv_10fdx)
if (adv_10hdx)
if (adv_pause)
if (adv_asym_pause)
/*
* Munge in any other fixed bits we require ...
*/
/*
* Restart the PHY and write the new values. Note the
* time, so that we can say whether subsequent link state
* changes can be attributed to our reprogramming the PHY
*/
return (DDI_FAILURE);
/*
* Enable the 'wire-speed' feature, if the chip supports it
* and we haven't got (any) loopback mode selected.
*/
case DEVICE_ID_5700:
case DEVICE_ID_5700x:
case DEVICE_ID_5705C:
case DEVICE_ID_5782:
/*
* These chips are known or assumed not to support it
*/
break;
default:
/*
* All other Broadcom chips are expected to support it.
*/
break;
}
#endif /* BGE_COPPER_WIRESPEED */
return (DDI_SUCCESS);
}
static boolean_t
{
/*
* Step 10: read the status from the PHY (which is self-clearing
* on read!); also read & clear the main (Ethernet) MAC status
* (the relevant bits of this are write-one-to-clear).
*/
BGE_DEBUG(("bge_check_copper: link %d/%s, MII status 0x%x "
"(was 0x%x), Ethernet MAC status 0x%x",
/*
* If the PHY status hasn't changed since last we looked, and
* we not forcing a recheck (i.e. the link state was already
* known), there's nothing to do.
*/
return (B_FALSE);
do {
/*
*/
/*
* We will only consider the link UP if all the readings
* are consistent and give meaningful results ...
*/
if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
} else {
}
BGE_DEBUG(("bge_check_copper: MII status 0x%x aux 0x%x "
"=> mode %d (%s)",
/*
* Record current register values, then reread status
* register & loop until it stabilises ...
*/
/*
* Assume very little ...
*/
if (bgep->param_adv_autoneg)
else
/*
* Discover all the link partner's abilities.
* These are scattered through various registers ...
*/
}
/*
* Step 12: update ndd-visible state parameters, BUT!
* we don't transfer the new state to <link_state> just yet;
* instead we mark the <link_state> as UNKNOWN, and our caller
* will resolve it once the status has stopped changing and
* been stable for several seconds.
*/
BGE_DEBUG(("bge_check_copper: link was %s speed %d duplex %d",
if (!linkup)
if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
} else {
}
} else {
}
BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d",
return (B_TRUE);
}
static const phys_ops_t copper_ops = {
};
/*
* ========== SerDes support ==========
*/
/*
* Reinitialise the SerDes interface. Note that it normally powers
* up in the disabled state, so we need to explicitly activate it.
*/
static int
{
/*
* Ensure that the main Ethernet MAC mode register is programmed
* appropriately for the SerDes interface ...
*/
if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
} else {
}
/*
* Ensure that loopback is OFF and comma detection is enabled. Then
* already be disabled). If we're shutting down, leave it disabled.
*/
if (powerdown)
return (DDI_SUCCESS);
/*
* Otherwise, pause, (re-)enable the SerDes output, and send
* all-zero config words in order to force autoneg restart.
* Invalidate the saved "link partners received configs", as
* we're starting over ...
*/
drv_usecwait(10000);
drv_usecwait(10);
bgep->serdes_status = ~0U;
return (DDI_SUCCESS);
}
/*
* Synchronise the SerDes speed/duplex/autonegotiation capabilities and
* advertisements with the required settings as specified by the various
* param_* variables that can be poked via the NDD interface.
*
* We always reinitalise the SerDes; this should cause the link to go down,
* and then back up again once the link is stable and autonegotiation
* (if enabled) is complete. We should get a link state change interrupt
* somewhere along the way ...
*
* param_* variables relating to lower speeds are ignored.
*
* NOTE: <genlock> must already be held by the caller
*/
static int
{
BGE_DEBUG(("bge_update_serdes: autoneg %d "
"pause %d asym_pause %d "
"1000fdx %d 1000hdx %d "
"100fdx %d 100hdx %d "
"10fdx %d 10hdx %d ",
/*
* SerDes settings are normally based on the param_* variables,
* but if any loopback mode is in effect, that takes precedence.
*
* BGE supports MAC-internal loopback, PHY-internal loopback,
* and External loopback at a variety of speeds (with a special
* cable). In all cases, autoneg is turned OFF, full-duplex
* is turned ON, and the speed/mastership is forced.
*
* Note: for the SerDes interface, "PHY" internal loopback is
* interpreted as SerDes internal loopback, and all external
*/
switch (bgep->param_loop_mode) {
case BGE_LOOP_NONE:
default:
break;
case BGE_LOOP_INTERNAL_PHY:
/* FALLTHRU */
case BGE_LOOP_INTERNAL_MAC:
case BGE_LOOP_EXTERNAL_1000:
case BGE_LOOP_EXTERNAL_100:
case BGE_LOOP_EXTERNAL_10:
break;
}
BGE_DEBUG(("bge_update_serdes: autoneg %d "
"pause %d asym_pause %d "
"1000fdx %d 1000hdx %d ",
/*
* We should have at least one gigabit technology capability
* set; if not, we select a default of 1000Mb/s full-duplex
*/
if (!adv_1000fdx && !adv_1000hdx)
/*
* Now transform the adv_* variables into the proper settings
* of the SerDes registers ...
*
* If autonegotiation is (now) not enabled, pretend it's been
* done and failed ...
*/
if (!adv_autoneg)
if (adv_1000fdx) {
}
if (adv_1000hdx) {
}
if (adv_pause)
if (adv_asym_pause)
/*
* Restart the SerDes and write the new values. Note the
* time, so that we can say whether subsequent link state
* changes can be attributed to our reprogramming the SerDes
*/
BGE_DEBUG(("bge_update_serdes: serdes |= 0x%x, advert 0x%x",
return (DDI_SUCCESS);
}
/*
* Bare-minimum autoneg protocol
*
* This code is only called when the link is up and we're receiving config
* words, which implies that the link partner wants to autonegotiate
* (otherwise, we wouldn't see configs and wouldn't reach this code).
*/
static void
{
if (!ack) {
/*
* Phase 1: after SerDes reset, we send a few zero configs
* but then stop. Here the partner is sending configs, but
* not ACKing ours; we assume that's 'cos we're not sending
* any. So here we send ours, with ACK already set.
*/
} else {
/*
* Phase 2: partner has ACKed our configs, so now we can
* stop sending; once our partner also stops sending, we
*/
}
BGE_DEBUG(("bge_autoneg_serdes: Rx 0x%x %s Tx 0x%x",
bgep->serdes_advert));
}
static boolean_t
{
for (;;) {
/*
* Step 10: BCM5714S, BCM5715S only
* Don't call function bge_autoneg_serdes() as
* RX_1000BASEX_AUTONEG_REG (0x0448) is not applicable
* to BCM5705, BCM5788, BCM5721, BCM5751, BCM5752,
* BCM5714, and BCM5715 devices.
*/
if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
if ((linkup && linkup_old) ||
(!linkup && !linkup_old)) {
break;
}
if (linkup)
linkup_old = B_TRUE;
else
} else {
/*
* Step 10: others
* read & clear the main (Ethernet) MAC status
* (the relevant bits of this are write-one-to-clear).
*/
BGE_DEBUG(("bge_check_serdes: link %d/%s, "
"MAC status 0x%x (was 0x%x)",
/*
* We will only consider the link UP if all the readings
* are consistent and give meaningful results ...
*/
/*
* Now some fiddling with the interpretation:
* if there's been an error at the PCS level, treat
* it as a link change (the h/w doesn't do this)
*
* if there's been a change, but it's only a PCS
* sync change (not a config change), AND the link
* already was & is still UP, then ignore the
* change
*/
emac_status &=
BGE_DEBUG(("bge_check_serdes: status 0x%x => 0x%x %s",
/*
* If we're receiving configs, run the autoneg protocol
*/
/*
* If the SerDes status hasn't changed, we're done ...
*/
break;
/*
* Go round again until we no longer see a change ...
*/
}
}
/*
* If we're not forcing a recheck (i.e. the link state was already
* known), and we didn't see the hardware flag a change, there's
* no more to do (and we tell the caller nothing happened).
*/
if (!recheck)
return (B_FALSE);
/*
* Don't resolve autoneg until we're no longer receiving configs
*/
return (B_FALSE);
/*
* Assume very little ...
*/
if (bgep->param_adv_autoneg)
else
/*
* Discover all the link partner's abilities.
*/
/*
* No fault, so derive partner's capabilities
*/
/*
* Pause direction resolution
*/
if (bgep->param_adv_pause &&
bgep->param_lp_pause) {
}
if (bgep->param_adv_asym_pause &&
if (bgep->param_adv_pause)
if (bgep->param_lp_pause)
}
}
/*
* Step 12: update ndd-visible state parameters, BUT!
* we don't transfer the new state to <link_state> just yet;
* instead we mark the <link_state> as UNKNOWN, and our caller
* will resolve it once the status has stopped changing and
* been stable for several seconds.
*/
BGE_DEBUG(("bge_check_serdes: link was %s speed %d duplex %d",
if (linkup) {
if (bgep->param_adv_1000fdx)
else
} else {
bgep->param_link_speed = 0;
}
BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d",
return (B_TRUE);
}
static const phys_ops_t serdes_ops = {
};
/*
* ========== Exported physical layer control routines ==========
*/
/*
* Here we have to determine which media we're using (copper or serdes).
* Once that's done, we can initialise the physical layer appropriately.
*/
int
{
/*
* Probe for the (internal) PHY. If it's not there, we'll assume
* that this is a 5703/4S, with a SerDes interface rather than
* BCM800x PHY.
*/
if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
if (regval & CPMU_STATUS_FUN_NUM)
if (regval & MEDIA_SELECTION_MODE)
}
if (bge_phy_probe(bgep)) {
} else {
}
return (EIO);
}
return (EIO);
}
return (0);
}
/*
* Reset the physical layer
*/
void
{
}
/*
* Reset and power off the physical layer.
*
* Another RESET should get it back to working, but it may take a few
* seconds it may take a few moments to return to normal operation ...
*/
int
{
}
/*
* Synchronise the PHYSICAL layer's speed/duplex/autonegotiation capabilities
* and advertisements with the required settings as specified by the various
* param_* variables that can be poked via the NDD interface.
*
* We always reset the PHYSICAL layer and reprogram *all* relevant registers.
* This is expected to cause the link to go down, and then back up again once
* the link is stable and autonegotiation (if enabled) is complete. We should
* get a link state change interrupt somewhere along the way ...
*
* NOTE: <genlock> must already be held by the caller
*/
int
{
}
/*
* Read the link status and determine whether anything's changed ...
*
* This routine should be called whenever the chip flags a change
* in the hardware link state.
*
* This routine returns B_FALSE if the link state has not changed,
* returns B_TRUE when the change to the new state should be accepted.
* In such a case, the param_* variables give the new hardware state,
* which the caller should use to update link_state etc.
*
* The caller must already hold <genlock>
*/
{
if (!recheck)
return (B_FALSE);
return (B_TRUE);
}