bge_chip2.c revision da14cebe459d3275048785f25bd869cb09b5307f
6185db853e024a486ff8837e6784dd290d866112dougm * CDDL HEADER START
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6185db853e024a486ff8837e6784dd290d866112dougm * You may not use this file except in compliance with the License.
6185db853e024a486ff8837e6784dd290d866112dougm * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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6185db853e024a486ff8837e6784dd290d866112dougm * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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6185db853e024a486ff8837e6784dd290d866112dougm * CDDL HEADER END
f345c0beb4c8f75cb54c2e070498e56febd468acdougm * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
6185db853e024a486ff8837e6784dd290d866112dougm * Use is subject to license terms.
6185db853e024a486ff8837e6784dd290d866112dougm#define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset)))
6185db853e024a486ff8837e6784dd290d866112dougm * Future features ... ?
6185db853e024a486ff8837e6784dd290d866112dougm * BGE MSI tunable:
6185db853e024a486ff8837e6784dd290d866112dougm * By default MSI is enabled on all supported platforms but it is disabled
6185db853e024a486ff8837e6784dd290d866112dougm * for some Broadcom chips due to known MSI hardware issues. Currently MSI
6185db853e024a486ff8837e6784dd290d866112dougm * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
6185db853e024a486ff8837e6784dd290d866112dougm * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
6185db853e024a486ff8837e6784dd290d866112dougm * Property names
6185db853e024a486ff8837e6784dd290d866112dougmstatic char knownids_propname[] = "bge-known-subsystems";
6185db853e024a486ff8837e6784dd290d866112dougm * Patchable globals:
6185db853e024a486ff8837e6784dd290d866112dougm * bge_autorecover
6185db853e024a486ff8837e6784dd290d866112dougm * Enables/disables automatic recovery after fault detection
6185db853e024a486ff8837e6784dd290d866112dougm * bge_mlcr_default
6185db853e024a486ff8837e6784dd290d866112dougm * Value to program into the MLCR; controls the chip's GPIO pins
6185db853e024a486ff8837e6784dd290d866112dougm * bge_dma_{rd,wr}prio
6185db853e024a486ff8837e6784dd290d866112dougm * Relative priorities of DMA reads & DMA writes respectively.
6185db853e024a486ff8837e6784dd290d866112dougm * These may each be patched to any value 0-3. Equal values
6185db853e024a486ff8837e6784dd290d866112dougm * will give "fair" (round-robin) arbitration for PCI access.
6185db853e024a486ff8837e6784dd290d866112dougm * Unequal values will give one or the other function priority.
6185db853e024a486ff8837e6784dd290d866112dougm * bge_dma_rwctrl
6185db853e024a486ff8837e6784dd290d866112dougm * Value to put in the Read/Write DMA control register. See
6185db853e024a486ff8837e6784dd290d866112dougm * the Broadcom PRM for things you can fiddle with in this
6185db853e024a486ff8837e6784dd290d866112dougm * register ...
6185db853e024a486ff8837e6784dd290d866112dougm * bge_{tx,rx}_{count,ticks}_{norm,intr}
6185db853e024a486ff8837e6784dd290d866112dougm * Send/receive interrupt coalescing parameters. Counts are
6185db853e024a486ff8837e6784dd290d866112dougm * #s of descriptors, ticks are in microseconds. *norm* values
6185db853e024a486ff8837e6784dd290d866112dougm * apply between status updates/interrupts; the *intr* values
6185db853e024a486ff8837e6784dd290d866112dougm * refer to the 'during-interrupt' versions - see the PRM.
6185db853e024a486ff8837e6784dd290d866112dougm * NOTE: these values have been determined by measurement. They
6185db853e024a486ff8837e6784dd290d866112dougm * differ significantly from the values recommended in the PRM.
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmuint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */
6185db853e024a486ff8837e6784dd290d866112dougm * Memory pool configuration parameters.
6185db853e024a486ff8837e6784dd290d866112dougm * These are generally specific to each member of the chip family, since
6185db853e024a486ff8837e6784dd290d866112dougm * each one may have a different memory size/configuration.
6185db853e024a486ff8837e6784dd290d866112dougm * Setting the mbuf pool length for a specific type of chip to 0 inhibits
6185db853e024a486ff8837e6784dd290d866112dougm * the driver from programming the various registers; instead they are left
6185db853e024a486ff8837e6784dd290d866112dougm * at their hardware defaults. This is the preferred option for later chips
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (5705+), whereas the older chips *required* these registers to be set,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * since the h/w default was 0 ;-(
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */
6185db853e024a486ff8837e6784dd290d866112dougm * Various high and low water marks, thresholds, etc ...
6185db853e024a486ff8837e6784dd290d866112dougm * Note: these are taken from revision 7 of the PRM, and some are different
6185db853e024a486ff8837e6784dd290d866112dougm * from both the values in earlier PRMs *and* those determined experimentally
6185db853e024a486ff8837e6784dd290d866112dougm * and used in earlier versions of this driver ...
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT;
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * bge_intr_max_loop controls the maximum loop number within bge_intr.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * When loading NIC with heavy network traffic, it is useful.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Increasing this value could have positive effect to throughput,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * but it might also increase ticks of a bge ISR stick on CPU, which might
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * lead to bad UI interactive experience. So tune this with caution.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * ========== Low-level chip & ring buffer manipulation ==========
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define BGE_DBG BGE_DBG_REGS /* debug flag for this code */
6185db853e024a486ff8837e6784dd290d866112dougm * Config space read-modify-write routines
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_cfg_clr16)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
6185db853e024a486ff8837e6784dd290d866112dougm#endif /* BGE_CFG_IO8 */
6185db853e024a486ff8837e6784dd290d866112dougmstatic void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_cfg_clr32)
6185db853e024a486ff8837e6784dd290d866112dougmbge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
6185db853e024a486ff8837e6784dd290d866112dougm * Indirect access to registers & RISC scratchpads, using config space
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * accesses only.
6185db853e024a486ff8837e6784dd290d866112dougm * This isn't currently used, but someday we might want to use it for
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * restoring the Subsystem Device/Vendor registers (which aren't directly
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * writable in Config Space), or for downloading firmware into the RISCs
6185db853e024a486ff8837e6784dd290d866112dougm * In any case there are endian issues to be resolved before this code is
6185db853e024a486ff8837e6784dd290d866112dougm * enabled; the bizarre way that bytes get twisted by this chip AND by
6185db853e024a486ff8837e6784dd290d866112dougm * the PCI bridge in SPARC systems mean that we shouldn't enable it until
6185db853e024a486ff8837e6784dd290d866112dougm * it's been thoroughly tested for all access sizes on all supported
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm * architectures (SPARC *and* x86!).
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougmuint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm#pragma inline(bge_ind_get32)
6185db853e024a486ff8837e6784dd290d866112dougm BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
330ef417fbd2286149a25e8033587edf7ae52ae5dougmvoid bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
330ef417fbd2286149a25e8033587edf7ae52ae5dougm#pragma inline(bge_ind_put32)
330ef417fbd2286149a25e8033587edf7ae52ae5dougmbge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
330ef417fbd2286149a25e8033587edf7ae52ae5dougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
330ef417fbd2286149a25e8033587edf7ae52ae5dougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* BGE_IND_IO32 */
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
330ef417fbd2286149a25e8033587edf7ae52ae5dougm#endif /* BGE_DEBUGGING */
6185db853e024a486ff8837e6784dd290d866112dougm * Perform first-stage chip (re-)initialisation, using only config-space
6185db853e024a486ff8837e6784dd290d866112dougm * accesses:
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm * + Read the vendor/device/revision/subsystem/cache-line-size registers,
6185db853e024a486ff8837e6784dd290d866112dougm * returning the data in the structure pointed to by <idp>.
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * + Configure the target-mode endianness (swap) options.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * + Disable interrupts and enable Memory Space accesses.
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * + Enable or disable Bus Mastering according to the <enable_dma> flag.
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * This sequence is adapted from Broadcom document 570X-PG102-R,
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * This function MUST be called before any non-config-space accesses
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * are made; on this first call <enable_dma> is B_FALSE, and it
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * effectively performs steps 3-1(!) of the initialisation sequence
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (the rest are not required but should be harmless).
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * It MUST also be called after a chip reset, as this disables
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and
330ef417fbd2286149a25e8033587edf7ae52ae5dougm * it is effectively performing steps 6-8.
330ef417fbd2286149a25e8033587edf7ae52ae5dougmvoid bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
330ef417fbd2286149a25e8033587edf7ae52ae5dougmbge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 3: save PCI cache line size and subsystem vendor ID
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Read all the config-space registers that characterise the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * chip, specifically vendor/device/revision/subsystem vendor
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and subsystem device id. We expect (but don't check) that
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Also save all bus-transaction related registers (cache-line
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * size, bus-grant/latency parameters, etc). Some of these are
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * cleared by reset, so we'll have to restore them later. This
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * comes from the Broadcom document 570X-PG102-R ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note: Broadcom document 570X-PG102-R seems to be in error
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * here w.r.t. the offsets of the Subsystem Vendor ID and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Subsystem (Device) ID registers, which are the opposite way
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * round according to the PCI standard. For good measure, we
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * save/restore both anyway.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
6185db853e024a486ff8837e6784dd290d866112dougm * Step 2 (also step 6): disable and clear interrupts.
6185db853e024a486ff8837e6784dd290d866112dougm * Steps 11-13: configure PIO endianness options, and enable
6185db853e024a486ff8837e6784dd290d866112dougm * indirect register access. We'll also select any other
6185db853e024a486ff8837e6784dd290d866112dougm * options controlled by the MHCR (e.g. tagged status, mask
6185db853e024a486ff8837e6784dd290d866112dougm * interrupt mode) at this stage ...
6185db853e024a486ff8837e6784dd290d866112dougm * Note: internally, the chip is 64-bit and BIG-endian, but
6185db853e024a486ff8837e6784dd290d866112dougm * since it talks to the host over a (LITTLE-endian) PCI bus,
6185db853e024a486ff8837e6784dd290d866112dougm * it normally swaps bytes around at the PCI interface.
6185db853e024a486ff8837e6784dd290d866112dougm * However, the PCI host bridge on SPARC systems normally
6185db853e024a486ff8837e6784dd290d866112dougm * swaps the byte lanes around too, since SPARCs are also
6185db853e024a486ff8837e6784dd290d866112dougm * BIG-endian. So it turns out that on SPARC, the right
6185db853e024a486ff8837e6784dd290d866112dougm * option is to tell the chip to swap (and the host bridge
6185db853e024a486ff8837e6784dd290d866112dougm * will swap back again), whereas on x86 we ask the chip
6185db853e024a486ff8837e6784dd290d866112dougm * NOT to swap, so the natural little-endianness of the
6185db853e024a486ff8837e6784dd290d866112dougm * PCI bus is assumed. Then the only thing that doesn't
6185db853e024a486ff8837e6784dd290d866112dougm * automatically work right is access to an 8-byte register
6185db853e024a486ff8837e6784dd290d866112dougm * by a little-endian host; but we don't want to set the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * accesses don't go where expected ;-( So we live with
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * that, and perform word-swaps in software in the few cases
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * where a chip register is defined as an 8-byte value --
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * see the code below for details ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * very clear in the register description in the PRM, but
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Broadcom document 570X-PG104-R page 248 explains a little
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * more (under "Broadcom Mask Mode"). The bit changes the way
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * way as the 5700 did, which isn't very convenient. Setting
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * bit do just what its name says -- MASK the PCI #INTA output
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (i.e. deassert the signal at the pin) leaving all internal
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * state unchanged. This is much more convenient for our
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * interrupt handler, so we set MASK_INTERRUPT_MODE here.
6185db853e024a486ff8837e6784dd290d866112dougm * Note: the inconvenient semantics of the interrupt mailbox
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (nonzero disables and acknowledges/clears the interrupt,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * zero enables AND CLEARS it) would make race conditions
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * likely in the interrupt handler:
6185db853e024a486ff8837e6784dd290d866112dougm * (1) acknowledge & disable interrupts
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (2) while (more to do)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * process packets
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (3) enable interrupts -- also clears pending
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * If the chip received more packets and internally generated
6185db853e024a486ff8837e6784dd290d866112dougm * an interrupt between the check at (2) and the mbox write
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * at (3), this interrupt would be lost :-(
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The best way to avoid this is to use TAGGED STATUS mode,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * where the chip includes a unique tag in each status block
6185db853e024a486ff8837e6784dd290d866112dougm * update, and the host, when re-enabling interrupts, passes
6185db853e024a486ff8837e6784dd290d866112dougm * the last tag it saw back to the chip; then the chip can
6185db853e024a486ff8837e6784dd290d866112dougm * see whether the host is truly up to date, and regenerate
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * its interrupt if not.
6185db853e024a486ff8837e6784dd290d866112dougm mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
6185db853e024a486ff8837e6784dd290d866112dougm#endif /* _BIG_ENDIAN */
6185db853e024a486ff8837e6784dd290d866112dougm * Step 1 (also step 7): Enable PCI Memory Space accesses
6185db853e024a486ff8837e6784dd290d866112dougm * Disable Memory Write/Invalidate
6185db853e024a486ff8837e6784dd290d866112dougm * Enable or disable Bus Mastering
6185db853e024a486ff8837e6784dd290d866112dougm * Note that all other bits are taken from the original value saved
6185db853e024a486ff8837e6784dd290d866112dougm * the first time through here, rather than from the current register
6185db853e024a486ff8837e6784dd290d866112dougm * value, 'cos that will have been cleared by a soft RESET since.
6185db853e024a486ff8837e6784dd290d866112dougm * In this way we preserve the OBP/nexus-parent's preferred settings
6185db853e024a486ff8837e6784dd290d866112dougm * of the parity-error and system-error enable bits across multiple
6185db853e024a486ff8837e6784dd290d866112dougm * chip RESETs.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * on BCM5714 revision A0, false parity error gets generated
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * due to a logic bug. Provide a workaround by disabling parity
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * On some PCI-E device, there were instances when
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the device was still link training.
6185db853e024a486ff8837e6784dd290d866112dougm * Clear any remaining error status bits
6185db853e024a486ff8837e6784dd290d866112dougm * Do following if and only if the device is NOT BCM5714C OR
6185db853e024a486ff8837e6784dd290d866112dougm * Make sure these indirect-access registers are sane
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * rather than random after power-up or reset
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
6185db853e024a486ff8837e6784dd290d866112dougm bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Distinguish CPU types
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * These use to distinguish AMD64 or Intel EM64T of CPU running mode.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * for PCI-Express based network interface card. This is the work-around
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * for those nics.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_get_em64t_type)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Operating register get/set access routines
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmuint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_reg_get32)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmvoid bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_reg_put32)
6185db853e024a486ff8837e6784dd290d866112dougmbge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
6185db853e024a486ff8837e6784dd290d866112dougm ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
6185db853e024a486ff8837e6784dd290d866112dougmvoid bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_reg_set32)
6185db853e024a486ff8837e6784dd290d866112dougmbge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
6185db853e024a486ff8837e6784dd290d866112dougmvoid bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_reg_clr32)
6185db853e024a486ff8837e6784dd290d866112dougmbge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_reg_get64)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
6185db853e024a486ff8837e6784dd290d866112dougm regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* _LITTLE_ENDIAN */
6185db853e024a486ff8837e6784dd290d866112dougmstatic void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_reg_put64)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* _LITTLE_ENDIAN */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
6185db853e024a486ff8837e6784dd290d866112dougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
6185db853e024a486ff8837e6784dd290d866112dougm * The DDI doesn't provide get/put functions for 128 bit data
6185db853e024a486ff8837e6784dd290d866112dougm * so we put RCBs out as two 64-bit chunks instead.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_reg_putrcb)
6185db853e024a486ff8837e6784dd290d866112dougmbge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
6185db853e024a486ff8837e6784dd290d866112dougm BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm p = (void *)rcbp;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmvoid bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_mbx_put)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Mailbox registers are nominally 64 bits on the 5701, but
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the MSW isn't used. On the 5703, they're only 32 bits
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * anyway. So here we just write the lower(!) 32 bits -
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * remembering that the chip is big-endian, even though the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * PCI bus is little-endian ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* _BIG_ENDIAN */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_mbx_get)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* _BIG_ENDIAN */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Blink all three LINK LEDs on simultaneously, then all off,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * then restore to automatic hardware control. This is used
6185db853e024a486ff8837e6784dd290d866112dougm * in laboratory testing to trigger a logic analyser or scope.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* BGE_DEBUGGING */
6185db853e024a486ff8837e6784dd290d866112dougm * NIC on-chip memory access routines
6185db853e024a486ff8837e6784dd290d866112dougm * Only 32K of NIC memory is visible at a time, controlled by the
6185db853e024a486ff8837e6784dd290d866112dougm * Memory Window Base Address Register (in PCI config space). Once
6185db853e024a486ff8837e6784dd290d866112dougm * this is set, the 32K region of NIC-local memory that it refers
6185db853e024a486ff8837e6784dd290d866112dougm * to can be directly addressed in the upper 32K of the 64K of PCI
6185db853e024a486ff8837e6784dd290d866112dougm * memory space used for the device.
6185db853e024a486ff8837e6784dd290d866112dougmstatic void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_nic_setwin)
6185db853e024a486ff8837e6784dd290d866112dougm * Don't do repeated zero data writes,
6185db853e024a486ff8837e6784dd290d866112dougm * if the device is BCM5714C/15C.
6185db853e024a486ff8837e6784dd290d866112dougm if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
6185db853e024a486ff8837e6784dd290d866112dougm /* Adjust lastWriteZeroData */
6185db853e024a486ff8837e6784dd290d866112dougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_nic_get32)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* workaround for word swap error */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmvoid bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_nic_put32)
6185db853e024a486ff8837e6784dd290d866112dougmbge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
6185db853e024a486ff8837e6784dd290d866112dougm /* workaround for word swap error */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
6185db853e024a486ff8837e6784dd290d866112dougm ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_nic_get64)
6185db853e024a486ff8837e6784dd290d866112dougm data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_nic_put64)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The DDI doesn't provide get/put functions for 128 bit data
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * so we put RCBs out as two 64-bit chunks instead.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_nic_putrcb)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
6185db853e024a486ff8837e6784dd290d866112dougm p = (void *)rcbp;
6185db853e024a486ff8837e6784dd290d866112dougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
6185db853e024a486ff8837e6784dd290d866112dougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
6185db853e024a486ff8837e6784dd290d866112dougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
6185db853e024a486ff8837e6784dd290d866112dougm ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
6185db853e024a486ff8837e6784dd290d866112dougmstatic void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_nic_zero)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
6185db853e024a486ff8837e6784dd290d866112dougm * MII (PHY) register get/set access routines
6185db853e024a486ff8837e6784dd290d866112dougm * These use the chip's MII auto-access method, controlled by the
6185db853e024a486ff8837e6784dd290d866112dougm * MII Communication register at 0x044c, so the CPU doesn't have
6185db853e024a486ff8837e6784dd290d866112dougm * to fiddle with the individual bits.
6185db853e024a486ff8837e6784dd290d866112dougm#define BGE_DBG BGE_DBG_MII /* debug flag for this code */
6185db853e024a486ff8837e6784dd290d866112dougmstatic uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
6185db853e024a486ff8837e6784dd290d866112dougmbge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Assemble the command ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Wait for any command already in progress ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note: this *shouldn't* ever find that there is a command
6185db853e024a486ff8837e6784dd290d866112dougm * in progress, because we already hold the <genlock> mutex.
6185db853e024a486ff8837e6784dd290d866112dougm * Nonetheless, we have sometimes seen the MI_COMMS_START
6185db853e024a486ff8837e6784dd290d866112dougm * bit set here -- it seems that the chip can initiate MII
6185db853e024a486ff8837e6784dd290d866112dougm * accesses internally, even with polling OFF.
6185db853e024a486ff8837e6784dd290d866112dougm regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
6185db853e024a486ff8837e6784dd290d866112dougm if (--timeout == 0)
6185db853e024a486ff8837e6784dd290d866112dougm return ((uint16_t)~0u);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm "MI_COMMS_START set for %d us; 0x%x->0x%x",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (--timeout == 0)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Drop out early if the READ FAILED bit is set -- this chip
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * could be a 5703/4S, with a SerDes instead of a PHY!
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return ((uint16_t)~0u);
6185db853e024a486ff8837e6784dd290d866112dougm return ((uint16_t)~0u);
6185db853e024a486ff8837e6784dd290d866112dougm * The PRM says to wait 5us after seeing the START bit clear
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and then re-read the register to get the final value of the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * data field, in order to avoid a race condition where the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * START bit is clear but the data field isn't yet valid.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note: we don't actually seem to be encounter this race;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * except when the START bit is seen set again (see below),
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the data field doesn't change during this 5us interval.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Unfortunately, when following the PRMs instructions above,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * we have occasionally seen the START bit set again(!) in the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * value read after the 5us delay. This seems to be due to the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * chip autonomously starting another MII access internally.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * In such cases, the command/data/etc fields relate to the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * internal command, rather than the one that we thought had
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * just finished. So in this case, we fall back to returning
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the data from the original read that showed START clear.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm "MI_COMMS_START set after transaction; 0x%x->0x%x",
6185db853e024a486ff8837e6784dd290d866112dougm return ((uint16_t)~0u);
6185db853e024a486ff8837e6784dd290d866112dougm return ((uint16_t)~0u);
6185db853e024a486ff8837e6784dd290d866112dougm return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
6185db853e024a486ff8837e6784dd290d866112dougmuint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
6185db853e024a486ff8837e6784dd290d866112dougm if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (0);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
6185db853e024a486ff8837e6784dd290d866112dougmvoid bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
6185db853e024a486ff8837e6784dd290d866112dougmbge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */
6185db853e024a486ff8837e6784dd290d866112dougm * Basic SEEPROM get/set access routine
6185db853e024a486ff8837e6784dd290d866112dougm * This uses the chip's SEEPROM auto-access method, controlled by the
6185db853e024a486ff8837e6784dd290d866112dougm * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
6185db853e024a486ff8837e6784dd290d866112dougm * doesn't have to fiddle with the individual bits.
6185db853e024a486ff8837e6784dd290d866112dougm * The caller should hold <genlock> and *also* have already acquired
6185db853e024a486ff8837e6784dd290d866112dougm * the right to access the SEEPROM, via bge_nvmem_acquire() above.
6185db853e024a486ff8837e6784dd290d866112dougm * Return value:
6185db853e024a486ff8837e6784dd290d866112dougm * 0 on success,
6185db853e024a486ff8837e6784dd290d866112dougm * ENODATA on access timeout (maybe retryable: device may just be busy)
6185db853e024a486ff8837e6784dd290d866112dougm * EPROTO on other h/w or s/w errors.
6185db853e024a486ff8837e6784dd290d866112dougm * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
6185db853e024a486ff8837e6784dd290d866112dougm * from a (successful) SEEPROM_ACCESS_READ.
6185db853e024a486ff8837e6784dd290d866112dougmstatic int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
6185db853e024a486ff8837e6784dd290d866112dougmbge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * On the newer chips that support both SEEPROM & Flash, we need
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * to specifically enable SEEPROM access (Flash is the default).
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * On older chips, we don't; SEEPROM is the only NVtype supported,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and the NVM control registers don't exist ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Check there's no command in progress.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note: this *shouldn't* ever find that there is a command
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * in progress, because we already hold the <genlock> mutex.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Also, to ensure we don't have a conflict with the chip's
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * internal firmware or a process accessing the same (shared)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * SEEPROM through the other port of a 5704, we've already
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * been through the "software arbitration" protocol.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * So this is just a final consistency check: we shouldn't
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * see EITHER the START bit (command started but not complete)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * OR the COMPLETE bit (command completed but not cleared).
6185db853e024a486ff8837e6784dd290d866112dougm regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
6185db853e024a486ff8837e6784dd290d866112dougm * Assemble the command ...
6185db853e024a486ff8837e6784dd290d866112dougm * By observation, a successful access takes ~20us on a 5703/4,
6185db853e024a486ff8837e6784dd290d866112dougm * but apparently much longer (up to 1000us) on the obsolescent
6185db853e024a486ff8837e6784dd290d866112dougm * BCM5700/BCM5701. We want to be sure we don't get any false
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * timeouts here; but OTOH, we don't want a bogus access to lock
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * out interrupts for longer than necessary. So we'll allow up
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * to 1000us ...
6185db853e024a486ff8837e6784dd290d866112dougm regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * All OK; read the SEEPROM data register, then write back
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the value read from the address register in order to
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * clear the <complete> bit and leave the SEEPROM access
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * state machine idle, ready for the next access ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (0);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Hmm ... what happened here?
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Most likely, the user addressed a non-existent SEEPROM. Or
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * maybe the SEEPROM was busy internally (e.g. processing a write)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and didn't respond to being addressed. Either way, it's left
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the SEEPROM access state machine wedged. So we'll reset it
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * before we leave, so it's ready for next time ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
6185db853e024a486ff8837e6784dd290d866112dougm * Basic Flash get/set access routine
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * These use the chip's Flash auto-access method, controlled by the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * fiddle with the individual bits.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The caller should hold <genlock> and *also* have already acquired
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the right to access the Flash, via bge_nvmem_acquire() above.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Return value:
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * 0 on success,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * ENODATA on access timeout (maybe retryable: device may just be busy)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * ENODEV if the NVmem device is missing or otherwise unusable
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * from a (successful) NVM_FLASH_CMD_RD.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * On the newer chips that support both SEEPROM & Flash, we need
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * to specifically disable SEEPROM access while accessing Flash.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The older chips don't support Flash, and the NVM registers don't
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * exist, so we shouldn't be here at all!
6185db853e024a486ff8837e6784dd290d866112dougm * Assemble the command ...
6185db853e024a486ff8837e6784dd290d866112dougm * Allow up to 1000ms ...
6185db853e024a486ff8837e6784dd290d866112dougm * All OK; read the data from the Flash read register
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
6185db853e024a486ff8837e6784dd290d866112dougm return (0);
6185db853e024a486ff8837e6784dd290d866112dougm * Hmm ... what happened here?
6185db853e024a486ff8837e6784dd290d866112dougm * Most likely, the user addressed a non-existent Flash. Or
6185db853e024a486ff8837e6784dd290d866112dougm * maybe the Flash was busy internally (e.g. processing a write)
6185db853e024a486ff8837e6784dd290d866112dougm * and didn't respond to being addressed. Either way, there's
6185db853e024a486ff8837e6784dd290d866112dougm * nothing we can here ...
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
6185db853e024a486ff8837e6784dd290d866112dougm * The next two functions regulate access to the NVram (if fitted).
6185db853e024a486ff8837e6784dd290d866112dougm * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
6185db853e024a486ff8837e6784dd290d866112dougm * (SPI) interface, but they can be accessed through either port. These
6185db853e024a486ff8837e6784dd290d866112dougm * are managed by different instance of this driver and have no software
6185db853e024a486ff8837e6784dd290d866112dougm * state in common.
6185db853e024a486ff8837e6784dd290d866112dougm * In addition (and even on a single core chip) the chip's internal
6185db853e024a486ff8837e6784dd290d866112dougm * firmware can access the SEEPROM/Flash, most notably after a RESET
6185db853e024a486ff8837e6784dd290d866112dougm * when it may download code to run internally.
6185db853e024a486ff8837e6784dd290d866112dougm * So we need to arbitrate between these various software agents. For
6185db853e024a486ff8837e6784dd290d866112dougm * this purpose, the chip provides the Software Arbitration Register,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * which implements hardware(!) arbitration.
549ec3fff108310966327d1dc9004551b63210b7dougm * This functionality didn't exist on older (5700/5701) chips, so there's
6185db853e024a486ff8837e6784dd290d866112dougm * nothing we can do by way of arbitration on those; also, if there's no
6185db853e024a486ff8837e6784dd290d866112dougm * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
6185db853e024a486ff8837e6784dd290d866112dougm * nothing to do.
6185db853e024a486ff8837e6784dd290d866112dougm * The internal firmware appears to use Request 0, which is the highest
6185db853e024a486ff8837e6784dd290d866112dougm * priority. So we'd like to use Request 2, leaving one higher and one
6185db853e024a486ff8837e6784dd290d866112dougm * lower for any future developments ... but apparently this doesn't
6185db853e024a486ff8837e6784dd290d866112dougm * always work. So for now, the code uses Request 1 ;-(
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * No arbitration performed, no release needed
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Our own request should be present (whether or not granted) ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * ... this will make it go away.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Arbitrate for access to the NVmem, if necessary
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Return value:
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * 0 on success
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * EAGAIN if the device is in use (retryable)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * ENODEV if the NVmem device is missing or otherwise unusable
6185db853e024a486ff8837e6784dd290d866112dougm * Access denied: no (recognisable) device fitted
6185db853e024a486ff8837e6784dd290d866112dougm * Access granted: no arbitration needed (or possible)
6185db853e024a486ff8837e6784dd290d866112dougm return (0);
6185db853e024a486ff8837e6784dd290d866112dougm * Access conditional: conduct arbitration protocol
6185db853e024a486ff8837e6784dd290d866112dougm * We're holding the per-port mutex <genlock>, so no-one other
6185db853e024a486ff8837e6784dd290d866112dougm * thread can be attempting to access the NVmem through *this*
6185db853e024a486ff8837e6784dd290d866112dougm * port. But it could be in use by the *other* port (of a 5704),
6185db853e024a486ff8837e6784dd290d866112dougm * or by the chip's internal firmware, so we have to go through
6185db853e024a486ff8837e6784dd290d866112dougm * the full (hardware) arbitration protocol ...
6185db853e024a486ff8837e6784dd290d866112dougm * Note that *because* we're holding <genlock>, the interrupt handler
6185db853e024a486ff8837e6784dd290d866112dougm * won't be able to progress. So we're only willing to spin for a
6185db853e024a486ff8837e6784dd290d866112dougm * fairly short time. Specifically:
6185db853e024a486ff8837e6784dd290d866112dougm * We *must* wait long enough for the hardware to resolve all
6185db853e024a486ff8837e6784dd290d866112dougm * requests and determine the winner. Fortunately, this is
6185db853e024a486ff8837e6784dd290d866112dougm * "almost instantaneous", even as observed by GHz CPUs.
6185db853e024a486ff8837e6784dd290d866112dougm * A successful access by another Solaris thread (via either
6185db853e024a486ff8837e6784dd290d866112dougm * port) typically takes ~20us. So waiting a bit longer than
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * that will give a good chance of success, if the other user
6185db853e024a486ff8837e6784dd290d866112dougm * *is* another thread on the other port.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * However, the internal firmware can hold on to the NVmem
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * for *much* longer: at least 10 milliseconds just after a
6185db853e024a486ff8837e6784dd290d866112dougm * RESET, and maybe even longer if the NVmem actually contains
6185db853e024a486ff8837e6784dd290d866112dougm * code to download and run on the internal CPUs.
6185db853e024a486ff8837e6784dd290d866112dougm * So, we'll allow 50us; if that's not enough then it's up to the
6185db853e024a486ff8837e6784dd290d866112dougm * caller to retry later (hence the choice of return code EAGAIN).
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (0);
6185db853e024a486ff8837e6784dd290d866112dougm * Somebody else must be accessing the NVmem, so abandon our
6185db853e024a486ff8837e6784dd290d866112dougm * attempt take control of it. The caller can try again later ...
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
6185db853e024a486ff8837e6784dd290d866112dougm * This code assumes that the GPIO1 bit has been wired up to the NVmem
549ec3fff108310966327d1dc9004551b63210b7dougm * write protect line in such a way that the NVmem is protected when
6185db853e024a486ff8837e6784dd290d866112dougm * GPIO1 is an input, or is an output but driven high. Thus, to make the
6185db853e024a486ff8837e6784dd290d866112dougm * NVmem writable we have to change GPIO1 to an output AND drive it low.
6185db853e024a486ff8837e6784dd290d866112dougm * Note: there's only one set of GPIO pins on a 5704, even though they
6185db853e024a486ff8837e6784dd290d866112dougm * can be accessed through either port. So the chip has to resolve what
6185db853e024a486ff8837e6784dd290d866112dougm * happens if the two ports program a single pin differently ... the rule
6185db853e024a486ff8837e6784dd290d866112dougm * it uses is that if the ports disagree about the *direction* of a pin,
6185db853e024a486ff8837e6784dd290d866112dougm * "output" wins over "input", but if they disagree about its *value* as
6185db853e024a486ff8837e6784dd290d866112dougm * an output, then the pin is TRISTATED instead! In such a case, no-one
6185db853e024a486ff8837e6784dd290d866112dougm * wins, and the external signal does whatever the external circuitry
6185db853e024a486ff8837e6784dd290d866112dougm * defines as the default -- which we've assumed is the PROTECTED state.
6185db853e024a486ff8837e6784dd290d866112dougm * So, we always change GPIO1 back to being an *input* whenever we're not
6185db853e024a486ff8837e6784dd290d866112dougm * specifically using it to unprotect the NVmem. This allows either port
6185db853e024a486ff8837e6784dd290d866112dougm * to update the NVmem, although obviously only one at a time!
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The caller should hold <genlock> and *also* have already acquired the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * right to access the NVmem, via bge_nvmem_acquire() above.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_nvmem_protect)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Now put it all together ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Try to acquire control of the NVmem; if successful, then:
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * unprotect it (if we want to write to it)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * perform the requested access
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * reprotect it (after a write)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * relinquish control
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Return value:
6185db853e024a486ff8837e6784dd290d866112dougm * 0 on success,
6185db853e024a486ff8837e6784dd290d866112dougm * EAGAIN if the device is in use (retryable)
6185db853e024a486ff8837e6784dd290d866112dougm * ENODATA on access timeout (maybe retryable: device may just be busy)
6185db853e024a486ff8837e6784dd290d866112dougm * ENODEV if the NVmem device is missing or otherwise unusable
6185db853e024a486ff8837e6784dd290d866112dougm * EPROTO on other h/w or s/w errors.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm switch (cmd) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Attempt to get a MAC address from the SEEPROM or Flash, if any
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (0ULL);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (0ULL);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (0ULL);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The Broadcom chip is natively BIG-endian, so that's how the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * MAC address is represented in NVmem. We may need to swap it
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * around on a little-endian host ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* _BIG_ENDIAN */
6185db853e024a486ff8837e6784dd290d866112dougm#else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
6185db853e024a486ff8837e6784dd290d866112dougm * Dummy version for when we're not supporting NVmem access
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_get_nvmac)
6185db853e024a486ff8837e6784dd290d866112dougm return (0ULL);
6185db853e024a486ff8837e6784dd290d866112dougm#endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
6185db853e024a486ff8837e6784dd290d866112dougm * Determine the type of NVmem that is (or may be) attached to this chip,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * We shouldn't get here; it means we don't recognise
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the chip, which means we don't know how to determine
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * what sort of NVmem (if any) it has. So we'll say
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * NONE, to disable the NVmem access code ...
6185db853e024a486ff8837e6784dd290d866112dougm * These devices support *only* SEEPROMs
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Initialize receive rule registers.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note that rules may persist across each bge_m_start/stop() call.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Using the values captured by bge_chip_cfg_init(), and additional probes
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * as required, characterise the chip fully: determine the label by which
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * to refer to this chip, the correct settings for various registers, and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * of course whether the device and/or subsystem are supported!
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm char buf[MAXPATHLEN]; /* any risk of stack overflow? */
6185db853e024a486ff8837e6784dd290d866112dougm * Check the PCI device ID to determine the generic chip type and
6185db853e024a486ff8837e6784dd290d866112dougm * select parameters that depend on this.
6185db853e024a486ff8837e6784dd290d866112dougm * Note: because the SPARC platforms in general don't fit the
6185db853e024a486ff8837e6784dd290d866112dougm * SEEPROM 'behind' the chip, the PCI revision ID register reads
549ec3fff108310966327d1dc9004551b63210b7dougm * as zero - which is why we use <asic_rev> rather than <revision>
6185db853e024a486ff8837e6784dd290d866112dougm * below ...
6185db853e024a486ff8837e6784dd290d866112dougm * Note: in general we can't distinguish between the Copper/SerDes
6185db853e024a486ff8837e6784dd290d866112dougm * versions by ID alone, as some Copper devices (e.g. some but not
6185db853e024a486ff8837e6784dd290d866112dougm * all 5703Cs) have the same ID as the SerDes equivalents. So we
6185db853e024a486ff8837e6784dd290d866112dougm * treat them the same here, and the MII code works out the media
6185db853e024a486ff8837e6784dd290d866112dougm * type later on ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Revision A0 of the 5703/5793 had various errata
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * that we can't or don't work around, so it's not
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * supported, but all later versions are
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
6185db853e024a486ff8837e6784dd290d866112dougm cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * This is nearly identical to the 5755M.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (Actually reports the 5755 chip ID.)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
6185db853e024a486ff8837e6784dd290d866112dougm cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Apart from the label, we treat this as a 5705(?)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Apart from the label, we treat this as a 5705(?)
549ec3fff108310966327d1dc9004551b63210b7dougm /* FALLTHRU */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Setup the default jumbo parameter.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * If jumbo is enabled and this kind of chipset supports jumbo feature,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * setup below jumbo specific parameters.
6185db853e024a486ff8837e6784dd290d866112dougm * For BCM5714/5715, there is only one standard receive ring. So the
6185db853e024a486ff8837e6784dd290d866112dougm * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
6185db853e024a486ff8837e6784dd290d866112dougm * feature is enabled.
f8825440532850af4790bbc685223958d4042844dougm sizeof (struct ether_header);
f8825440532850af4790bbc685223958d4042844dougm * Identify the NV memory type: SEEPROM or Flash?
f8825440532850af4790bbc685223958d4042844dougm * Now, we want to check whether this device is part of a
f8825440532850af4790bbc685223958d4042844dougm * supported subsystem (e.g., on the motherboard of a Sun
f8825440532850af4790bbc685223958d4042844dougm * branded platform).
f8825440532850af4790bbc685223958d4042844dougm * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
f8825440532850af4790bbc685223958d4042844dougm * Rule 2: If it's on the list on known subsystems, then it's OK.
f8825440532850af4790bbc685223958d4042844dougm * Note: 0x14e41647 should *not* appear in the list, but the code
f8825440532850af4790bbc685223958d4042844dougm * doesn't enforce that.
f8825440532850af4790bbc685223958d4042844dougm err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
f8825440532850af4790bbc685223958d4042844dougm * Got the list; scan for a matching subsystem vendor/device
f8825440532850af4790bbc685223958d4042844dougm while (i--)
6185db853e024a486ff8837e6784dd290d866112dougm * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
6185db853e024a486ff8837e6784dd290d866112dougm * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
6185db853e024a486ff8837e6784dd290d866112dougm * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore,
6185db853e024a486ff8837e6784dd290d866112dougm * we have to check specially for the exact device paths to the
549ec3fff108310966327d1dc9004551b63210b7dougm * motherboard devices on those platforms ;-(
6185db853e024a486ff8837e6784dd290d866112dougm * Note: we can't just use the "supported-subsystems" mechanism
6185db853e024a486ff8837e6784dd290d866112dougm * above, because the entry would have to be 0x14e41647 -- which
6185db853e024a486ff8837e6784dd290d866112dougm * would then accept *any* plugin card that *didn't* contain a
6185db853e024a486ff8837e6784dd290d866112dougm * (valid) SEEPROM ;-(
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */
f8825440532850af4790bbc685223958d4042844dougm * Now check what we've discovered: is this truly a supported
f8825440532850af4790bbc685223958d4042844dougm * chip on (the motherboard of) a supported platform?
f8825440532850af4790bbc685223958d4042844dougm * Possible problems here:
f8825440532850af4790bbc685223958d4042844dougm * 1) it's a completely unheard-of chip (e.g. 5761)
f8825440532850af4790bbc685223958d4042844dougm * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
f8825440532850af4790bbc685223958d4042844dougm * 3) it's a chip we would support if it were on the motherboard
f8825440532850af4790bbc685223958d4042844dougm * of a Sun platform, but this one isn't ;-(
6185db853e024a486ff8837e6784dd290d866112dougm "Device 'pci%04x,%04x' not recognized (%d?)",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm "Device 'pci%04x,%04x' (%d) revision %d not supported",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm "%d-based subsystem 'pci%04x,%04x' not validated",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm return (0);
6185db853e024a486ff8837e6784dd290d866112dougm * Various registers that control the chip's internal engines (state
549ec3fff108310966327d1dc9004551b63210b7dougm * machines) have a <reset> and <enable> bits (fortunately, in the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * same place in each such register :-).
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * To reset the state machine, the <reset> bit must be written with 1;
6185db853e024a486ff8837e6784dd290d866112dougm * it will then read back as 1 while the reset is in progress, but
6185db853e024a486ff8837e6784dd290d866112dougm * self-clear to 0 when the reset completes.
6185db853e024a486ff8837e6784dd290d866112dougm * To enable a state machine, one must set the <enable> bit, which
6185db853e024a486ff8837e6784dd290d866112dougm * will continue to read back as 0 until the state machine is running.
6185db853e024a486ff8837e6784dd290d866112dougm * To disable a state machine, the <enable> bit must be cleared, but
6185db853e024a486ff8837e6784dd290d866112dougm * it will continue to read back as 1 until the state machine actually
6185db853e024a486ff8837e6784dd290d866112dougm * This routine implements polling for completion of a reset, enable
6185db853e024a486ff8837e6784dd290d866112dougm * or disable operation, returning B_TRUE on success (bit reached the
549ec3fff108310966327d1dc9004551b63210b7dougm * required state) or B_FALSE on timeout (200*100us == 20ms).
6185db853e024a486ff8837e6784dd290d866112dougmstatic boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
6185db853e024a486ff8837e6784dd290d866112dougm for (n = 200; n; --n) {
f8825440532850af4790bbc685223958d4042844dougm * Various registers that control the chip's internal engines (state
f8825440532850af4790bbc685223958d4042844dougm * machines) have a <reset> bit (fortunately, in the same place in
f8825440532850af4790bbc685223958d4042844dougm * each such register :-). To reset the state machine, this bit must
f8825440532850af4790bbc685223958d4042844dougm * be written with 1; it will then read back as 1 while the reset is
f8825440532850af4790bbc685223958d4042844dougm * in progress, but self-clear to 0 when the reset completes.
f8825440532850af4790bbc685223958d4042844dougm * This code sets the bit, then polls for it to read back as zero.
f8825440532850af4790bbc685223958d4042844dougm * The return value is B_TRUE on success (reset bit cleared itself),
f8825440532850af4790bbc685223958d4042844dougm * or B_FALSE if the state machine didn't recover :(
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * NOTE: the Core reset is similar to other resets, except that we
6185db853e024a486ff8837e6784dd290d866112dougm * can't poll for completion, since the Core reset disables memory
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * access! So we just have to assume that it will all complete in
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
6185db853e024a486ff8837e6784dd290d866112dougm * BCM5714/5721/5751 pcie chip special case. In order to avoid
6185db853e024a486ff8837e6784dd290d866112dougm * resetting PCIE block and bringing PCIE link down, bit 29
6185db853e024a486ff8837e6784dd290d866112dougm * in the register needs to be set first, and then set it again
6185db853e024a486ff8837e6784dd290d866112dougm * while the reset bit is written.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * See:P500 of 57xx-PG102-RDS.pdf.
6185db853e024a486ff8837e6784dd290d866112dougm * Special case - causes Core reset
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * On SPARC v9 we want to ensure that we don't start
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * timing until the I/O access has actually reached
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the chip, otherwise we might make the next access
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * too early. And we can't just force the write out
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * by following it with a read (even to config space)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * because that would cause the fault we're trying
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * to avoid. Hence the need for membar_sync() here.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* __sparcv9 */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * On some platforms,system need about 300us for
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * link setup.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* PCI-E device need more reset time */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* Set PCIE max payload size and clear error status. */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Various registers that control the chip's internal engines (state
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * machines) have an <enable> bit (fortunately, in the same place in
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * each such register :-). To stop the state machine, this bit must
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * be written with 0, then polled to see when the state machine has
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * actually stopped.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The return value is B_TRUE on success (enable bit cleared), or
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * B_FALSE if the state machine didn't stop :(
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmstatic boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
6185db853e024a486ff8837e6784dd290d866112dougm * For Schumacher's bugfix CR6490108
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Not quite like the others; it doesn't
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * have an <enable> bit, but instead we
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * have to set and then clear all the bits
6185db853e024a486ff8837e6784dd290d866112dougm * Various registers that control the chip's internal engines (state
6185db853e024a486ff8837e6784dd290d866112dougm * machines) have an <enable> bit (fortunately, in the same place in
6185db853e024a486ff8837e6784dd290d866112dougm * each such register :-). To start the state machine, this bit must
6185db853e024a486ff8837e6784dd290d866112dougm * be written with 1, then polled to see when the state machine has
6185db853e024a486ff8837e6784dd290d866112dougm * actually started.
6185db853e024a486ff8837e6784dd290d866112dougm * The return value is B_TRUE on success (enable bit set), or
6185db853e024a486ff8837e6784dd290d866112dougm * B_FALSE if the state machine didn't start :(
6185db853e024a486ff8837e6784dd290d866112dougmstatic boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
6185db853e024a486ff8837e6784dd290d866112dougm * Not quite like the others; it doesn't
6185db853e024a486ff8837e6784dd290d866112dougm * have an <enable> bit, but instead we
6185db853e024a486ff8837e6784dd290d866112dougm * have to set and then clear all the bits
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Reprogram the Ethernet, Transmit, and Receive MAC
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * modes to match the param_* variables
6185db853e024a486ff8837e6784dd290d866112dougm * Reprogram the Ethernet MAC mode ...
6185db853e024a486ff8837e6784dd290d866112dougm macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
6185db853e024a486ff8837e6784dd290d866112dougm * ... the Transmit MAC mode ...
6185db853e024a486ff8837e6784dd290d866112dougm macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
6185db853e024a486ff8837e6784dd290d866112dougm * ... and the Receive MAC mode
6185db853e024a486ff8837e6784dd290d866112dougm macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * bge_chip_sync() -- program the chip with the unicast MAC address,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the multicast hash table, the required level of promiscuity, and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the current loopback mode ...
6185db853e024a486ff8837e6784dd290d866112dougmint bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
6185db853e024a486ff8837e6784dd290d866112dougm void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * If the TX/RX MAC engines are already running, we should stop
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * them (and reset the RX engine) before changing the parameters.
6185db853e024a486ff8837e6784dd290d866112dougm * If they're not running, this will have no effect ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * NOTE: this is currently disabled by default because stopping
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and restarting the Tx engine may cause an outgoing packet in
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * transit to be truncated. Also, stopping and restarting the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Rx engine seems to not work correctly on the 5705. Testing
6185db853e024a486ff8837e6784dd290d866112dougm * has not (yet!) revealed any problems with NOT stopping and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * restarting these engines (and Broadcom say their drivers don't
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * do this), but if it is found to cause problems, this variable
6185db853e024a486ff8837e6784dd290d866112dougm * can be patched to re-enable the old behaviour ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Reprogram the hashed multicast address table ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Transform the MAC address(es) from host to chip format, then
6185db853e024a486ff8837e6784dd290d866112dougm * reprogram the transmit random backoff seed and the unicast
6185db853e024a486ff8837e6784dd290d866112dougm * MAC address(es) ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm "setting MAC address %012llx",
6185db853e024a486ff8837e6784dd290d866112dougm * Set or clear the PROMISCUOUS mode bit
549ec3fff108310966327d1dc9004551b63210b7dougm (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
6185db853e024a486ff8837e6784dd290d866112dougm * Sync the rest of the MAC modes too ...
549ec3fff108310966327d1dc9004551b63210b7dougm * Restart RX/TX MAC engines if required ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * This array defines the sequence of state machine control registers
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * in which the <enable> bit must be cleared to bring the chip to a
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * clean stop. Taken from Broadcom document 570X-PG102-R, p116.
6185db853e024a486ff8837e6784dd290d866112dougm * This function is called by bge_quiesce(). We
6185db853e024a486ff8837e6784dd290d866112dougm * turn off all the DMA engines here.
6185db853e024a486ff8837e6784dd290d866112dougm * Flag that no more activity may be initiated
6185db853e024a486ff8837e6784dd290d866112dougm * bge_chip_stop() -- stop all chip processing
6185db853e024a486ff8837e6784dd290d866112dougm * If the <fault> parameter is B_TRUE, we're stopping the chip because
6185db853e024a486ff8837e6784dd290d866112dougm * we've detected a problem internally; otherwise, this is a normal
6185db853e024a486ff8837e6784dd290d866112dougm * (clean) stop (at user request i.e. the last STREAM has been closed).
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * When driver try to shutdown the BCM5705/5788/5721/5751/
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * 5752/5714 and 5715 chipsets,the buffer manager and the mem
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * -ory arbiter should not be disabled.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Finally, disable (all) MAC events & clear the MAC status
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * if we're stopping the chip because of a detected fault then do
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * appropriate actions
6185db853e024a486ff8837e6784dd290d866112dougm * need to free buffers in case the fault was
6185db853e024a486ff8837e6784dd290d866112dougm * due to a memory error in a buffer - got to
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * do a fair bit of tidying first
6185db853e024a486ff8837e6784dd290d866112dougm * Poll for completion of chip's ROM firmware; also, at least on the
6185db853e024a486ff8837e6784dd290d866112dougm * first time through, find and return the hardware MAC address, if any.
6185db853e024a486ff8837e6784dd290d866112dougm * Step 19: poll for firmware completion (GENCOMM port set
6185db853e024a486ff8837e6784dd290d866112dougm * to the ones complement of T3_MAGIC_NUMBER).
6185db853e024a486ff8837e6784dd290d866112dougm * While we're at it, we also read the MAC address register;
6185db853e024a486ff8837e6784dd290d866112dougm * at some stage the firmware will load this with the
6185db853e024a486ff8837e6784dd290d866112dougm * factory-set value.
6185db853e024a486ff8837e6784dd290d866112dougm * When both the magic number and the MAC address are set,
6185db853e024a486ff8837e6784dd290d866112dougm * we're done; but we impose a time limit of one second
6185db853e024a486ff8837e6784dd290d866112dougm * (1000*1000us) in case the firmware fails in some fashion
6185db853e024a486ff8837e6784dd290d866112dougm * or the SEEPROM that provides that MAC address isn't fitted.
6185db853e024a486ff8837e6784dd290d866112dougm * After the first time through (chip state != INITIAL), we
6185db853e024a486ff8837e6784dd290d866112dougm * don't need the MAC address to be set (we've already got it
6185db853e024a486ff8837e6784dd290d866112dougm * or not, from the first time), so we don't wait for it, but
6185db853e024a486ff8837e6784dd290d866112dougm * we still have to wait for the T3_MAGIC_NUMBER.
6185db853e024a486ff8837e6784dd290d866112dougm * Note: the magic number is only a 32-bit quantity, but the NIC
6185db853e024a486ff8837e6784dd290d866112dougm * memory is 64-bit (and big-endian) internally. Addressing the
6185db853e024a486ff8837e6784dd290d866112dougm * GENCOMM word as "the upper half of a 64-bit quantity" makes
6185db853e024a486ff8837e6784dd290d866112dougm * it work correctly on both big- and little-endian hosts.
6185db853e024a486ff8837e6784dd290d866112dougm for (i = 0; i < 1000; ++i) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm (void *)bgep, i));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm for (i = 0; i < 1000; ++i) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Maximum times of trying to get the NVRAM access lock
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * by calling bge_nvmem_acquire()
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmbge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
6185db853e024a486ff8837e6784dd290d866112dougm BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Do we need to stop the chip cleanly before resetting?
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
6185db853e024a486ff8837e6784dd290d866112dougm bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
6185db853e024a486ff8837e6784dd290d866112dougm * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
6185db853e024a486ff8837e6784dd290d866112dougm * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
6185db853e024a486ff8837e6784dd290d866112dougm * Before reset Core clock,it is
6185db853e024a486ff8837e6784dd290d866112dougm * also required to initialize the Memory Arbiter as specified in step9
6185db853e024a486ff8837e6784dd290d866112dougm * and Misc Host Control Register as specified in step-13
6185db853e024a486ff8837e6784dd290d866112dougm * Step 4-5: reset Core clock & wait for completion
6185db853e024a486ff8837e6784dd290d866112dougm * Steps 6-8: are done by bge_chip_cfg_init()
549ec3fff108310966327d1dc9004551b63210b7dougm * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
6185db853e024a486ff8837e6784dd290d866112dougm if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* _BIG_ENDIAN */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * NVRAM Corruption Workaround
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
6185db853e024a486ff8837e6784dd290d866112dougm * Step 8a: This may belong elsewhere, but BCM5721 needs
549ec3fff108310966327d1dc9004551b63210b7dougm * a bit set to avoid a fifo overflow/underflow bug.
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
6185db853e024a486ff8837e6784dd290d866112dougm * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * not be changed.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 10-11: configure PIO endianness options and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * enable indirect register access -- already done
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 12-13: enable writing to the PCI state & clock
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * control registers -- not required; we aren't going to
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * use those features.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 14-15: Configure DMA endianness options. See
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the comments on the setting of the MHCR above.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif /* _BIG_ENDIAN */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* Wait for NVRAM init */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm (i < 10000)) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 16-17: poll for firmware completion
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 18: enable external memory -- doesn't apply.
6185db853e024a486ff8837e6784dd290d866112dougm * However we take the opportunity to set the MLCR anyway, as
6185db853e024a486ff8837e6784dd290d866112dougm * this register also controls the SEEPROM auto-access method
6185db853e024a486ff8837e6784dd290d866112dougm * which we may want to use later ...
6185db853e024a486ff8837e6784dd290d866112dougm * The proper value here depends on the way the chip is wired
6185db853e024a486ff8837e6784dd290d866112dougm * into the circuit board, as this register *also* controls which
6185db853e024a486ff8837e6784dd290d866112dougm * of the "Miscellaneous I/O" pins are driven as outputs and the
6185db853e024a486ff8837e6784dd290d866112dougm * values driven onto those pins!
6185db853e024a486ff8837e6784dd290d866112dougm * See also step 74 in the PRM ...
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
6185db853e024a486ff8837e6784dd290d866112dougm * Step 20: clear the Ethernet MAC mode register
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 21: restore cache-line-size, latency timer, and
6185db853e024a486ff8837e6784dd290d866112dougm * subsystem ID registers to their original values (not
6185db853e024a486ff8837e6784dd290d866112dougm * those read into the local structure <chipid>, 'cos
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * that was after they were cleared by the RESET).
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note: the Subsystem Vendor/Device ID registers are not
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * directly writable in config space, so we use the shadow
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * copy in "Page Zero" of register space to restore them
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * both in one go ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
6185db853e024a486ff8837e6784dd290d866112dougm pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The SEND INDEX registers should be reset to zero by the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * global chip reset; if they're not, there'll be trouble
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * later on.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (sx0 != 0) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
6185db853e024a486ff8837e6784dd290d866112dougm /* Enable MSI code */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * On the first time through, save the factory-set MAC address
549ec3fff108310966327d1dc9004551b63210b7dougm * (if any). If bge_poll_firmware() above didn't return one
6185db853e024a486ff8837e6784dd290d866112dougm * (from a chip register) consider looking in the attached NV
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * memory device, if any. Once we have it, we save it in both
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * register-image (64-bit) and byte-array forms. All-zero and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * all-one addresses are not valid, and we refuse to stash those.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm for (i = ETHERADDRL; i-- != 0; ) {
6185db853e024a486ff8837e6784dd290d866112dougm * Record the new state
6185db853e024a486ff8837e6784dd290d866112dougm * bge_chip_start() -- start the chip transmitting and/or receiving,
6185db853e024a486ff8837e6784dd290d866112dougm * including enabling interrupts
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Taken from Broadcom document 570X-PG102-R, pp 102-116.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The document specifies 95 separate steps to fully
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * initialise the chip!!!!
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * The reset code above has already got us as far as step
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * 21, so we continue with ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 22: clear the MAC statistics block
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (0x0300-0x0aff in NIC-local memory)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 23: clear the status block (in host memory)
6185db853e024a486ff8837e6784dd290d866112dougm * Step 24: set DMA read/write control register
6185db853e024a486ff8837e6784dd290d866112dougm pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 25: Configure DMA endianness -- already done (16/17)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 26: Configure Host-Based Send Rings
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 27: Indicate Host Stack Up
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 28: Configure checksum options:
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Solaris supports the hardware default checksum options.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Workaround for Incorrect pseudo-header checksum calculation.
6185db853e024a486ff8837e6784dd290d866112dougm * Step 29: configure Timer Prescaler. The value is always the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * same: the Core Clock frequency in MHz (66), minus 1, shifted
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * for the whole chip!
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* put PHY into ready state */
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
6185db853e024a486ff8837e6784dd290d866112dougm (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
6185db853e024a486ff8837e6784dd290d866112dougm * Steps 30-31: Configure MAC local memory pool & DMA pool registers
6185db853e024a486ff8837e6784dd290d866112dougm * If the mbuf_length is specified as 0, we just leave these at
6185db853e024a486ff8837e6784dd290d866112dougm * their hardware defaults, rather than explicitly setting them.
6185db853e024a486ff8837e6784dd290d866112dougm * As the Broadcom HRM,driver better not change the parameters
6185db853e024a486ff8837e6784dd290d866112dougm * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 32: configure MAC memory pool watermarks
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 33: configure DMA resource watermarks
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 34-36: enable buffer manager & internal h/w queues
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 37-39: initialise Receive Buffer (Producer) RCBs
6185db853e024a486ff8837e6784dd290d866112dougm * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
6185db853e024a486ff8837e6784dd290d866112dougm bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
6185db853e024a486ff8837e6784dd290d866112dougm * Steps 41-43: clear Send Ring Producer Indices and initialise
6185db853e024a486ff8837e6784dd290d866112dougm * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 44-45: initialise Receive Return Rings
6185db853e024a486ff8837e6784dd290d866112dougm * (0x0200-0x02ff in NIC-local memory)
6185db853e024a486ff8837e6784dd290d866112dougm * Step 46: initialise Receive Buffer (Producer) Ring indexes
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 47: configure the MAC unicast address
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 48: configure the random backoff seed
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 96: set up multicast filters
6185db853e024a486ff8837e6784dd290d866112dougm * Step 49: configure the MTU
6185db853e024a486ff8837e6784dd290d866112dougm * Step 50: configure the IPG et al
f345c0beb4c8f75cb54c2e070498e56febd468acdougm bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
6185db853e024a486ff8837e6784dd290d866112dougm * Step 51: configure the default Rx Return Ring
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 52-54: configure Receive List Placement,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and enable Receive List Placement Statistics
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 55-56: enable Send Data Initiator Statistics
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 57-58: stop (?) the Host Coalescing Engine
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 59-62: initialise Host Coalescing parameters
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm);
6185db853e024a486ff8837e6784dd290d866112dougm * Steps 63-64: initialise status block & statistics
6185db853e024a486ff8837e6784dd290d866112dougm * host memory addresses
6185db853e024a486ff8837e6784dd290d866112dougm * The statistic block does not exist in some chipsets
6185db853e024a486ff8837e6784dd290d866112dougm * Step 65: initialise Statistics Coalescing Tick Counter
6185db853e024a486ff8837e6784dd290d866112dougm * Steps 66-67: initialise status block & statistics
6185db853e024a486ff8837e6784dd290d866112dougm * NIC-local memory addresses
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 68-71: start the Host Coalescing Engine, the Receive BD
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Completion Engine, the Receive List Placement Engine, and the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and BCM5715.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
6185db853e024a486ff8837e6784dd290d866112dougm if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
6185db853e024a486ff8837e6784dd290d866112dougm * Step 72: Enable MAC DMA engines
6185db853e024a486ff8837e6784dd290d866112dougm * Step 73: Clear & enable MAC statistics
6185db853e024a486ff8837e6784dd290d866112dougm * Step 74: configure the MLCR (Miscellaneous Local Control
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Register); not required, as we set up the MLCR in step 10
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (part of the reset code) above.
6185db853e024a486ff8837e6784dd290d866112dougm * Step 75: clear Interrupt Mailbox 0
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Steps 76-87: Gentlemen, start your engines ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Enable the DMA Completion Engine, the Write DMA Engine,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the Read DMA Engine, Receive Data Completion Engine,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the MBuf Cluster Free Engine, the Send Data Completion Engine,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the Send BD Completion Engine, the Receive BD Initiator Engine,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the Receive Data Initiator Engine, the Send Data Initiator Engine,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the Send BD Initiator Engine, and the Send BD Selector Engine.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Beware exhaust fumes?
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
6185db853e024a486ff8837e6784dd290d866112dougm if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
6185db853e024a486ff8837e6784dd290d866112dougm if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
6185db853e024a486ff8837e6784dd290d866112dougm if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
6185db853e024a486ff8837e6784dd290d866112dougm * Step 88: download firmware -- doesn't apply
6185db853e024a486ff8837e6784dd290d866112dougm * Steps 89-90: enable Transmit & Receive MAC Engines
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
6185db853e024a486ff8837e6784dd290d866112dougm if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
6185db853e024a486ff8837e6784dd290d866112dougm if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
6185db853e024a486ff8837e6784dd290d866112dougm * Step 91: disable auto-polling of PHY status
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 92: configure D0 power state (not required)
6185db853e024a486ff8837e6784dd290d866112dougm * Step 93: initialise LED control register ()
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Switch to 5700 (MAC) mode on these older chips
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 94: activate link
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 95: set up physical layer (PHY/SerDes)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * restart autoneg (if required)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Extra step (DSG): hand over all the Receive Buffers to the chip
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * MSI bits:The least significant MSI 16-bit word.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * ISR will be triggered different.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Extra step (DSG): select which interrupts are enabled
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Program the Ethernet MAC engine to signal attention on
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Link Change events, then enable interrupts on MAC, DMA,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * and FLOW attention signals.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Step 97: enable PCI interrupts!!!
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * All done!
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * ========== Hardware interrupt handler ==========
6185db853e024a486ff8837e6784dd290d866112dougm#define BGE_DBG BGE_DBG_INT /* debug flag for this code */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Sync the status block, then atomically clear the specified bits in
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the <flags-and-tag> field of the status block.
6185db853e024a486ff8837e6784dd290d866112dougm * the <flags> word of the status block, returning the value of the
6185db853e024a486ff8837e6784dd290d866112dougm * <tag> and the <flags> before the bits were cleared.
6185db853e024a486ff8837e6784dd290d866112dougmstatic int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
6185db853e024a486ff8837e6784dd290d866112dougm#pragma inline(bge_status_sync)
6185db853e024a486ff8837e6784dd290d866112dougmbge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
6185db853e024a486ff8837e6784dd290d866112dougm retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#pragma inline(bge_wake_factotum)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * bge_intr() -- handle chip interrupts
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * GLD v2 checks that s/w setup is complete before passing
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * interrupts to this routine, thus eliminating the old
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * (and well-known) race condition around ddi_add_intr()
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Check whether chip's says it's asserting #INTA;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * if not, don't process or claim the interrupt.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Note that the PCI signal is active low, so the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * bit is *zero* when the interrupt is asserted.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Block further PCI interrupts ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Check MSI status
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
6185db853e024a486ff8837e6784dd290d866112dougm * Sync the status block and grab the flags-n-tag from it.
6185db853e024a486ff8837e6784dd290d866112dougm * We count the number of interrupts where there doesn't
6185db853e024a486ff8837e6784dd290d866112dougm * seem to have been a DMA update of the status block; if
6185db853e024a486ff8837e6784dd290d866112dougm * it *has* been updated, the counter will be cleared in
6185db853e024a486ff8837e6784dd290d866112dougm * the while() loop below ...
6185db853e024a486ff8837e6784dd290d866112dougm for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
6185db853e024a486ff8837e6784dd290d866112dougm * bge_chip_stop() may have freed dma area etc
6185db853e024a486ff8837e6784dd290d866112dougm * while we were in this interrupt handler -
6185db853e024a486ff8837e6784dd290d866112dougm * better not call bge_status_sync()
6185db853e024a486ff8837e6784dd290d866112dougm * Tell the chip that we're processing the interrupt
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Drop the mutex while we:
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Receive any newly-arrived packets
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Recycle any newly-finished send buffers
6185db853e024a486ff8837e6784dd290d866112dougm * Tell the chip we've finished processing, and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * give it the tag that we got from the status
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * block earlier, so that it knows just how far
6185db853e024a486ff8837e6784dd290d866112dougm * we've gone. If it's got more for us to do,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * it will now update the status block and try
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * to assert an interrupt (but we've got the
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * #INTA blocked at present). If we see the
6185db853e024a486ff8837e6784dd290d866112dougm * update, we'll loop around to do some more.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Eventually we'll get out of here ...
6185db853e024a486ff8837e6784dd290d866112dougm * Check for exceptional conditions that we need to handle
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Link status changed
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Status block not updated
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * Probably due to the internal status tag not
6185db853e024a486ff8837e6784dd290d866112dougm * being reset. Force a status block update now;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * this should ensure that we get an update and
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * a new interrupt. After that, we should be in
6185db853e024a486ff8837e6784dd290d866112dougm * sync again ...
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * If this happens multiple times in a row,
6185db853e024a486ff8837e6784dd290d866112dougm * it means DMA is just not working. Maybe
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * the chip's failed, or maybe there's a
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * problem on the PCI bus or in the host-PCI
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * bridge (Tomatillo).
6185db853e024a486ff8837e6784dd290d866112dougm * At all events, we want to stop further
6185db853e024a486ff8837e6784dd290d866112dougm * interrupts and let the recovery code take
6185db853e024a486ff8837e6784dd290d866112dougm * over to see whether anything can be done
6185db853e024a486ff8837e6784dd290d866112dougm * about it ...
6185db853e024a486ff8837e6784dd290d866112dougm * Reenable assertion of #INTA, unless there's a DMA fault
6185db853e024a486ff8837e6784dd290d866112dougm if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
6185db853e024a486ff8837e6784dd290d866112dougm if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * We must stop ASF heart beat before
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * bge_chip_stop(), otherwise some
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * computers (ex. IBM HS20 blade
6185db853e024a486ff8837e6784dd290d866112dougm * server) may crash.
return (result);
static boolean_t
return (B_FALSE);
case LINK_STATE_UP:
case LINK_STATE_DOWN:
if (check)
return (check);
static boolean_t
return (B_FALSE);
#if !defined(BGE_NETCONSOLE)
return (B_TRUE);
int dma_state;
return (DDI_INTR_UNCLAIMED);
case BGE_CHIP_RUNNING:
if (error)
case BGE_CHIP_ERROR:
case BGE_CHIP_FAULT:
if (bge_autorecover) {
return (result);
DDI_FM_OK) {
DDI_FM_OK) {
#ifdef BGE_IPMI_ASF
* genlock to call bge_receive/bge_recycle. Can't stop the chip at
#ifdef BGE_IPMI_ASF
if (linkchg) {
return (result);
case BGE_CHIP_RUNNING:
case BGE_CHIP_FAULT:
case BGE_CHIP_ERROR:
void *regaddr;
void *regaddr;
void *regaddr;
void *regaddr;
#if BGE_SEE_IO32
int err;
#if BGE_FLASH_IO32
int err;
void *vaddr;
void *vaddr;
static enum ioc_reply
switch (cmd) {
return (IOC_INVAL);
case BGE_PEEK:
case BGE_POKE:
return (IOC_INVAL);
return (IOC_INVAL);
return (IOC_INVAL);
case BGE_PP_SPACE_CFG:
mem_va = 0;
case BGE_PP_SPACE_REG:
mem_va = 0;
case BGE_PP_SPACE_NIC:
mem_va = 0;
case BGE_PP_SPACE_MII:
mem_va = 0;
#if BGE_SEE_IO32
case BGE_PP_SPACE_SEEPROM:
mem_va = 0;
#if BGE_FLASH_IO32
case BGE_PP_SPACE_FLASH:
mem_va = 0;
case BGE_PP_SPACE_BGE:
case BGE_PP_SPACE_STATUS:
case BGE_PP_SPACE_STATISTICS:
case BGE_PP_SPACE_TXDESC:
case BGE_PP_SPACE_TXBUFF:
case BGE_PP_SPACE_RXDESC:
case BGE_PP_SPACE_RXBUFF:
case BGE_PP_SPACE_TXDESC:
case BGE_PP_SPACE_TXBUFF:
case BGE_PP_SPACE_RXDESC:
case BGE_PP_SPACE_RXBUFF:
case BGE_PP_SPACE_STATUS:
case BGE_PP_SPACE_STATISTICS:
return (IOC_INVAL);
return (IOC_INVAL);
return (IOC_INVAL);
return (IOC_INVAL);
return (IOC_INVAL);
static enum ioc_reply
switch (cmd) {
return (IOC_INVAL);
case BGE_DIAG:
return (IOC_ACK);
case BGE_PEEK:
case BGE_POKE:
case BGE_PHY_RESET:
return (IOC_RESTART_ACK);
case BGE_SOFT_RESET:
case BGE_HARD_RESET:
return (IOC_ACK);
static enum ioc_reply
return (IOC_INVAL);
return (IOC_INVAL);
return (IOC_INVAL);
switch (cmd) {
return (IOC_INVAL);
case BGE_MII_READ:
return (IOC_REPLY);
case BGE_MII_WRITE:
return (IOC_ACK);
#if BGE_SEE_IO32
static enum ioc_reply
return (IOC_INVAL);
return (IOC_INVAL);
return (IOC_INVAL);
switch (cmd) {
return (IOC_INVAL);
case BGE_SEE_READ:
case BGE_SEE_WRITE:
return (IOC_REPLY);
#if BGE_FLASH_IO32
static enum ioc_reply
return (IOC_INVAL);
return (IOC_INVAL);
return (IOC_INVAL);
switch (cmd) {
return (IOC_INVAL);
case BGE_FLASH_READ:
case BGE_FLASH_WRITE:
return (IOC_REPLY);
enum ioc_reply
int cmd;
switch (cmd) {
return (IOC_INVAL);
case BGE_DIAG:
case BGE_PEEK:
case BGE_POKE:
case BGE_PHY_RESET:
case BGE_SOFT_RESET:
case BGE_HARD_RESET:
return (IOC_INVAL);
case BGE_MII_READ:
case BGE_MII_WRITE:
#if BGE_SEE_IO32
case BGE_SEE_READ:
case BGE_SEE_WRITE:
#if BGE_FLASH_IO32
case BGE_FLASH_READ:
case BGE_FLASH_WRITE:
#ifdef NOT_YET
#ifdef BGE_IPMI_ASF
#ifndef __sparc
return (data);
tries = 0;
tries ++;
switch (mode) {
case BGE_INIT_RESET:
case BGE_SHUTDOWN_RESET:
case BGE_SUSPEND_RESET:
switch (mode) {
case BGE_INIT_RESET:
case BGE_SHUTDOWN_RESET:
case BGE_SUSPEND_RESET:
switch (mode) {
case BGE_INIT_RESET:
case BGE_SHUTDOWN_RESET: