audioens.h revision 88447a05f537aabe9a1bc3d5313f22581ec992a7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
*/
/*
* This file is part of Open Sound System
*
* Copyright (C) 4Front Technologies 1996-2008.
*
* This software is released under CDDL 1.0 source license.
* See the COPYING file included in the main directory of this source
* distribution for the license terms and conditions.
*/
#ifndef _AUDIOENS_H
#define _AUDIOENS_H
/* CONCERT PCI-SIG defines */
#define CONC_PCI_VENDID 0x1274U
#define CONC_PCI_DEVID 0x1371U
/* Concert97 direct register offset defines */
/* Concert memory page-banked register offset defines */
/* Concert memory page number defines */
/* SPDIF defines - only newer chips */
/* PCM format defines */
#define CONC_PCM_DAC1_STEREO 0x01
#define CONC_PCM_DAC1_16BIT 0x02
#define CONC_PCM_DAC2_STEREO 0x04
#define CONC_PCM_DAC2_16BIT 0x08
#define CONC_PCM_ADC_STEREO 0x10
#define CONC_PCM_ADC_16BIT 0x20
/* Device Control defines */
/* Misc Control defines */
/* Serial Control defines */
#define CONC_SERCTL_ADCLOOP 0x80
#define CONC_SERCTL_DAC2LOOP 0x40
#define CONC_SERCTL_DAC1LOOP 0x20
/* Interrupt Status defines */
#define CONC_STATUS_SPDIF_MASK 0x18000000
#define CONC_STATUS_SPDIF_P1P2 0x00000000
#define CONC_STATUS_SPDIF_P1 0x08000000
#define CONC_STATUS_SPDIF_P2 0x10000000
#define CONC_STATUS_SPDIF_REC 0x18000000
#define CONC_STATUS_ECHO 0x04000000
#define CONC_STATUS_SPKR_MASK 0x03000000
#define CONC_STATUS_SPKR_2CH 0x00000000
#define CONC_STATUS_SPKR_4CH 0x01000000
#define CONC_STATUS_SPKR_P1 0x02000000
#define CONC_STATUS_SPKR_P2 0x03000000
#define CONC_STATUS_EN_SPDIF 0x00040000
/* JOYCTL register defines */
#define CONC_JOYCTL_200 0x00
#define CONC_JOYCTL_208 0x01
#define CONC_JOYCTL_210 0x02
#define CONC_JOYCTL_218 0x03
#define CONC_JOYCTL_SPDIFEN_B 0x04
#define CONC_JOYCTL_RECEN_B 0x08
/* UARTCSTAT register masks */
#define CONC_UART_RXRDY 0x01
#define CONC_UART_TXRDY 0x02
#define CONC_UART_TXINT 0x04
#define CONC_UART_RXINT 0x80
#define CONC_UART_CTL 0x03
#define CONC_UART_TXINTEN 0x20
#define CONC_UART_RXINTEN 0x80
/* defines for the CONCERT97 Sample Rate Converters */
#define SRC_DAC1_FIFO 0x00
#define SRC_DAC2_FIFO 0x20
#define SRC_ADC_FIFO 0x40
#define SRC_ADC_VOL_L 0x6c
#define SRC_ADC_VOL_R 0x6d
#define SRC_DAC1_BASE 0x70
#define SRC_DAC2_BASE 0x74
#define SRC_ADC_BASE 0x78
#define SRC_DAC1_VOL_L 0x7c
#define SRC_DAC1_VOL_R 0x7d
#define SRC_DAC2_VOL_L 0x7e
#define SRC_DAC2_VOL_R 0x7f
#define SRC_TRUNC_N_OFF 0x00
#define SRC_INT_REGS_OFF 0x01
#define SRC_ACCUM_FRAC_OFF 0x02
#define SRC_VFREQ_FRAC_OFF 0x03
/* miscellaneous control defines */
#define SRC_IOPOLL_COUNT 0x20000UL
#define SRC_CTLMASK 0x00780000UL
#endif /* _AUDIOENS_H */