audioemu10k.h revision 992413f4053d9470046876b234fe094062b730b7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
*/
/*
* Copyright (C) 4Front Technologies 1996-2009.
*/
#ifndef EMU10K_H
#define EMU10K_H
#define PCI_VENDOR_ID_CREATIVE 0x1102
#define PCI_DEVICE_ID_SBLIVE 0x0002
#define PCI_DEVICE_ID_AUDIGY 0x0004
#define PCI_DEVICE_ID_AUDIGYVALUE 0x0008
#define SAMPLE_RATE 48000
#define EMU10K_NAME "audioemu10k"
#define EMU10K_NUM_PORTC 2
#define EMU10K_PLAY 0
#define EMU10K_REC 1
#define EMU10K_MAX_INTRS 512
#define EMU10K_MIN_INTRS 10
#define EMU10K_INTRS 100
#define FRAGMENT_FRAMES 512
#define EMU10K1_MAGIC 0xe10001
#define EMU10K2_MAGIC 0xe10002
/* Audio */
/* Audio buffer + silent page */
/* Wall clock register */
#define WC 0x10
/* Hardware config register */
#define HCFG 0x14
#define HCFG_AUTOMUTE 0x00000010
#define HCFG_LOCKSOUNDCACHE 0x00000008
#define HCFG_LOCKTANKCACHE_MASK 0x00000004
#define HCFG_LOCKTANKCACHE 0x01020014
#define A_HCFG_VMUTE 0x00004000
#define A_HCFG_AUTOMUTE 0x00008000
/*
* GPIO bit definitions (global register 0x18) for Audigy.
*/
/* Status bits (read only) */
#define GPIO_FRONTPLUGGED 0x4000
#define GPIO_REARPLUGGED 0x8000
#define GPIO_HEADPHPLUGGED 0x0100
#define GPIO_ANALOG_MUTE 0x0040
#define FILL_PAGE_MAP_ENTRY(e, v) \
/*
* Audio block registers
*/
#define CPF_CURRENTPITCH_MASK 0xffff0000
#define CPF_CURRENTPITCH 0x10100000
#define CPF_STEREO_MASK 0x00008000
#define CPF_STOP_MASK 0x00004000
#define CPF_FRACADDRESS_MASK 0x00003fff
#define PTRX_PITCHTARGET_MASK 0xffff0000
#define PTRX_PITCHTARGET 0x10100001
#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00
#define PTRX_FXSENDAMOUNT_A 0x08080001
#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff
#define PTRX_FXSENDAMOUNT_B 0x08000001
#define CCR 0x009
#define CCR_CACHEINVALIDSIZE 0x07190009
#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000
#define CCR_CACHELOOPFLAG 0x01000000
#define CCR_INTERLEAVEDSAMPLES 0x00800000
#define CCR_WORDSIZEDSAMPLES 0x00400000
#define CCR_READADDRESS 0x06100009
#define CCR_READADDRESS_MASK 0x003f0000
#define CCR_LOOPINVALSIZE 0x0000fe00
#define CCR_LOOPFLAG 0x00000100
#define CCR_CACHELOOPADDRHI 0x000000ff
#define CLP 0x00a
#define SRHE 0x07c
#define STHE 0x07d
#define SRDA 0x07e
#define STDA 0x07f
#define L_FXRT 0x00b
#define MAPA 0x00c
#define MAPB 0x00d
#define PEFE_PITCHAMOUNT 0x0808001a
#define PEFE_FILTERAMOUNT 0x0800001a
#define CSBA 0x4c
#define CSDC 0x4d
#define CSFE 0x4e
#define CSHG 0x4f
#define AC97SLOT 0x05f
#define AC97SLOT_REAR_RIGHT 0x01
#define AC97SLOT_REAR_LEFT 0x02
#define AC97SLOT_CENTER 0x10
#define AC97SLOT_LFE 0x20
/* Half loop interrupt registers (audigy only) */
/* Interrupt pending register */
#define INTPEND 0x08
#define INT_VI 0x00100000
#define INT_VD 0x00080000
#define INT_MU 0x00040000
#define INT_MF 0x00020000
#define INT_MH 0x00010000
#define INT_AF 0x00008000
#define INT_AH 0x00004000
#define INT_IT 0x00000200
#define INT_TX 0x00000100
#define INT_RX 0x00000080
#define INT_CL 0x00000040
/* Interrupt enable register */
#define IE 0x0c
#define IE_VI 0x00000400
#define IE_VD 0x00000200
#define IE_MU 0x00000100
#define IE_MB 0x00000080
#define IE_AB 0x00000040
#define IE_IT 0x00000004
#define IE_TX 0x00000002
#define IE_RX 0x00000001
/* Interval timer register */
#define TIMR 0x1a
/* EMU10K2 MIDI UART */
#define MUADAT 0x070
#define MUACMD 0x071
#define SPRI 0x6a
#define SPRA 0x6b
#define SPRC 0x6c
#define SRHE 0x07c
#define STHE 0x07d
#define SRDA 0x07e
#define MAX_GPR 256
/* See feature_mask below */
#define SB_LIVE 1
#define SB_AUDIGY 2
#define SB_AUDIGY2 4
#define SB_AUDIGY2VAL 8
#define SB_51 0x10
#define SB_71 0x20
#define LEFT_CH 0
#define RIGHT_CH 1
#ifdef _KERNEL
typedef struct _emu10k_devc_t emu10k_devc_t;
typedef struct _emu10k_portc_t emu10k_portc_t;
typedef enum {
CTL_VOLUME = 0,
/* monitor source values */
/* this one must be last */
typedef struct _emu10k_ctrl {
int gpr_num;
typedef struct _emu10k_gpr {
} emu10k_gpr_t;
struct _emu10k_portc_t {
/* Helper functions */
void (*update_port)(emu10k_portc_t *);
void (*reset_port)(emu10k_portc_t *);
void (*stop_port)(emu10k_portc_t *);
void (*start_port)(emu10k_portc_t *);
int channels;
unsigned fragfr;
unsigned nframes;
unsigned nfrags;
unsigned fragsz;
/* Start of loop within the internal memory space */
int syncdir;
/* Position & timing */
int dopos;
};
struct _emu10k_devc_t {
/*
* Page table
*/
/*
* Silent page used by voices that don't play anything.
*/
/*
* Device feature mask tells which kind of features are
* supported by the hardware. Audigy2/2val have multiple bits
* set while Live! has just the SB_LIVE bits. So Features of
*/
int feature_mask;
/*
* Mixer
*/
/*
* Audio
*/
int audio_memptr;
int *silent_page;
};
#endif /* _KERNEL */
#endif /* EMU10K_H */