7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
3caf11144eab1a56717f986d44ae7f40ee8b28fcxc * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Use is subject to license terms.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * All rights reserved.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Redistribution and use in source and binary forms, with or without
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * modification, are permitted provided that the following conditions
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * are met:
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 1. Redistributions of source code must retain the above copyright
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * notice, this list of conditions and the following disclaimer,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * without modification.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 2. Redistributions in binary form must reproduce at minimum a disclaimer
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * redistribution must be conditioned upon including a substantially
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * similar Disclaimer requirement for further binary redistribution.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 3. Neither the names of the above-listed copyright holders nor the names
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * of any contributors may be used to endorse or promote products derived
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * from this software without specific prior written permission.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NO WARRANTY
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * THE POSSIBILITY OF SUCH DAMAGES.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ath_impl.h is a bridge between the HAL and the driver. It
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * defines some data structures encapsulating the HAL interface
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * and communicating with the IEEE80211 MAC layer and other
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * driver components.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifndef _ATH_IMPL_H
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define _ATH_IMPL_H
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifdef __cplusplus
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern "C" {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Defintions for the Atheros Wireless LAN controller driver.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#include <sys/note.h>
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#include <sys/list.h>
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#include <sys/net80211.h>
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#include "ath_hal.h"
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
a399b7655a1d835aa8606c2b29e4e777baac8635zf/* Bit map related macros. */
a399b7655a1d835aa8606c2b29e4e777baac8635zf#define setbit(a, i) ((a)[(i)/NBBY] |= (1 << ((i)%NBBY)))
a399b7655a1d835aa8606c2b29e4e777baac8635zf#define clrbit(a, i) ((a)[(i)/NBBY] &= ~(1 << ((i)%NBBY)))
a399b7655a1d835aa8606c2b29e4e777baac8635zf#define isset(a, i) ((a)[(i)/NBBY] & (1 << ((i)%NBBY)))
a399b7655a1d835aa8606c2b29e4e777baac8635zf#define isclr(a, i) (!((a)[(i)/NBBY] & (1 << ((i)%NBBY))))
a399b7655a1d835aa8606c2b29e4e777baac8635zf
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Bit flags in the ath_dbg_flags
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_INIT 0x00000001 /* initialisation */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_GLD 0x00000002 /* GLD entry points */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_HAL 0x00000004 /* HAL related code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_INT 0x00000008 /* interrupt handler */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_RECV 0x00000010 /* receive-side code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_SEND 0x00000020 /* packet-send code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_80211 0x00000040 /* 80211 state machine */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_IOCTL 0x00000080 /* ioctl code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_STATS 0x00000100 /* statistics */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_RATE 0x00000200 /* rate control */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_AUX 0x00000400 /* for ath_aux.c */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_WIFICFG 0x00000800 /* wificonfig */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_OSDEP 0x00001000 /* osdep */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_ATTACH 0x00002000 /* attach */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_DETACH 0x00004000 /* detach */
f11a3086bc0b6b242d387296efedd61d43316e8dxc#define ATH_DBG_SUSPEND 0x00008000 /* suspend/resume */
f11a3086bc0b6b242d387296efedd61d43316e8dxc#define ATH_DBG_ALL 0x0000ffff /* all */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifdef DEBUG
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DDB(command) do { \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc { command; } \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc _NOTE(CONSTANTCONDITION)\
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc } while (0)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#else
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DDB(command)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif /* DEBUG */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Node type of wifi device
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifndef DDI_NT_NET_WIFI
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define DDI_NT_NET_WIFI "ddi_network:wifi"
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_NODENAME "ath"
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DEBUG(args) ATH_DDB(ath_dbg args)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_LE_READ_4(p) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((uint32_t) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((((uint8_t *)(p))[0]) | (((uint8_t *)(p))[1] << 8) | \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_N(a) (sizeof (a) / sizeof (a[0]))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXQ_SETUP(asc, i) ((asc)->asc_txqsetup & (1<<i))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_PA2DESC(_asc, _pa) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((struct ath_desc *)((caddr_t)(_asc)->asc_desc + \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((_pa) - (_asc)->asc_desc_dma.cookie.dmac_address)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Sync a DMA area described by a dma_area_t
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (area).offset, (area).alength, (flag)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXINTR_PERIOD 5
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TIMEOUT 1000
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_RXBUF 80 /* number of RX buffers */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXBUF 200 /* number of TX buffers */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXDESC 1 /* number of descriptors per buffer */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
3caf11144eab1a56717f986d44ae7f40ee8b28fcxc#define ATH_MCHASH 64 /* multicast hash table size */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
1f156c6a7686102f9a1057cb9294c57041f3da68xc#define ATH_DEF_CACHE_BYTES 32 /* default cache line size */
1f156c6a7686102f9a1057cb9294c57041f3da68xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* driver-specific node state */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_node {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ieee80211_node an_node; /* base class */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t an_tx_times; /* rate ctl times on one rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t an_tx_ok; /* tx ok pkt */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t an_tx_err; /* tx !ok pkt */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t an_tx_retr; /* tx retry count */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int32_t an_tx_upper; /* tx upper rate req cnt */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t an_tx_antenna; /* antenna for last good frame */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rix0; /* series 0 rate index */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_try0; /* series 0 try count */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_mgtratesp; /* short preamble h/w rate for " " */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate0; /* series 0 h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate1; /* series 1 h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate2; /* series 2 h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate3; /* series 3 h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate0sp; /* series 0 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate1sp; /* series 1 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate2sp; /* series 2 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate3sp; /* series 3 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_NODE(_n) ((struct ath_node *)(_n))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_stats {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_hardware; /* fatal hardware error interrupts */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rxorn; /* rx overrun interrupts */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rxeol; /* rx eol interrupts */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_txurn; /* tx underrun interrupts */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_mgmt; /* management frames transmitted */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_discard; /* frames discarded prior to assoc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_invalid; /* frames discarded 'cuz device gone */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_qstop; /* tx queue stopped 'cuz full */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_nobufmgt; /* tx failed 'cuz no tx buffer(mgmt) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_xretries; /* tx failed 'cuz too many retries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_filtered; /* tx failed 'cuz xmit filtered */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_shortretry; /* tx on-chip retries (short) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_longretry; /* tx on-chip retries (long) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_noack; /* tx frames with no ack marked */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_rts; /* tx frames with rts enabled */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_shortpre; /* tx frames with short preamble */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_altrate; /* tx frames with alternate rate */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ast_tx_protect; /* tx frames with protection */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int16_t ast_tx_rssi; /* tx rssi of last ack */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int16_t ast_tx_rssidelta; /* tx rssi delta */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_badcrypt; /* rx failed 'cuz decryption */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_phyerr; /* rx PHY error summary count */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_phy[32]; /* rx PHY error per-code counts */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_tooshort; /* rx discarded 'cuz frame too short */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_per_cal; /* periodic calibration calls */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_per_calfail; /* periodic calibration failed */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_per_rfgain; /* periodic calibration rfgain reset */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rate_calls; /* rate control checks */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rate_raise; /* rate control raised xmit rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rate_drop; /* rate control dropped xmit rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Describes one chunk of allocated DMA-able memory
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * In some cases, this is a single chunk as allocated from the system;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * but we also use this structure to represent slices carved off such
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * a chunk. Even when we don't really need all the information, we
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * use this structure as a convenient way of correlating the various
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ways of looking at a piece of memory (kernel VA, IO space DVMA,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * handle+offset, etc).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct dma_area {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ddi_acc_handle_t acc_hdl; /* handle for memory */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc caddr_t mem_va; /* CPU VA of memory */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t nslots; /* number of slots */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t size; /* size per slot */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc size_t alength; /* allocated size */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* >= product of above */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ddi_dma_handle_t dma_hdl; /* DMA handle */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc offset_t offset; /* relative to handle */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ddi_dma_cookie_t cookie; /* associated cookie */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ncookies; /* must be 1 */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t token; /* arbitrary identifier */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc}; /* 0x50 (80) bytes */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct dma_area dma_area_t;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_buf {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int bf_flags; /* tx descriptor flags */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_desc *bf_desc; /* virtual addr of desc */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China struct ath_desc_status bf_status; /* tx/rx status */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t bf_daddr; /* physical addr of desc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc dma_area_t bf_dma; /* dma area for buf */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China mblk_t *bf_m; /* message for buf */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ieee80211_node *bf_in; /* pointer to the node */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* we're in list of asc->asc_txbuf_list or asc->asc_rxbuf_list */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc list_node_t bf_node;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Data transmit queue state. One of these exists for each
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * hardware transmit queue. Packets sent to us from above
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * are assigned to queues based on their priority. Not all
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * devices support a complete set of hardware transmit queues.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * For those devices the array sc_ac2q will map multiple
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * priorities to fewer hardware queues (typically all to one
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * hardware queue).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_txq {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint_t axq_qnum; /* hardware q number */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint_t axq_depth; /* queue depth (stat only) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint_t axq_intrcnt; /* interrupt count */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t *axq_link; /* link ptr in last TX desc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc list_t axq_list; /* transmit queue */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc kmutex_t axq_lock; /* lock on q and link */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * asc_isc must be the first element, for convience of
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * casting between iee80211com and ath
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct ath {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ieee80211com_t asc_isc; /* IEEE 802.11 common */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc dev_info_t *asc_dev; /* back pointer to dev_info_t */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China ddi_taskq_t *asc_tq; /* private task queue */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_hal *asc_ah; /* Atheros HAL */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t asc_invalid : 1, /* being detached */
f11a3086bc0b6b242d387296efedd61d43316e8dxc asc_isrunning : 1, /* device is operational */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc asc_mrretry : 1, /* multi-rate retry support */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc asc_have11g : 1, /* have 11g support */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc asc_splitmic : 1, /* Split TKIP mic keys */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc asc_hasclrkey: 1; /* CLR key supported */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_RATE_TABLE *asc_rates[IEEE80211_MODE_MAX]; /* h/w rate */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t asc_protrix; /* protect rate index */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t asc_mcastantenna; /* Multicast antenna number */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ddi_acc_handle_t asc_cfg_handle; /* DDI I/O handle */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ddi_acc_handle_t asc_io_handle; /* DDI I/O handle */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t asc_cachelsz; /* cache line size */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ddi_iblock_cookie_t asc_iblock;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ddi_softintr_t asc_softint_id;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_desc *asc_desc; /* TX/RX descriptors */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc dma_area_t asc_desc_dma; /* descriptor structure */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* pointer to the first "struct ath_buf" */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_buf *asc_vbufptr;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* length of all allocated "struct ath_buf" */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t asc_vbuflen;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* size of one DMA TX/RX buffer based on 802.11 MTU */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int32_t asc_dmabuf_size;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc list_t asc_rxbuf_list;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc kmutex_t asc_rxbuflock; /* recv lock for above data */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t *asc_rxlink; /* link ptr in last RX desc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t asc_rx_pend;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint64_t asc_lastrx; /* tsf at last rx'd frame */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc list_t asc_txbuf_list;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc kmutex_t asc_txbuflock; /* txbuf lock */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint_t asc_txqsetup; /* h/w queues setup */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_txq asc_txq[HAL_NUM_TX_QUEUES]; /* tx queues */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_txq *asc_ac2q[5]; /* WME AC -> h/w qnum */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_RATE_TABLE *asc_currates; /* current rate table */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc enum ieee80211_phymode asc_curmode; /* current phy mode */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CHANNEL asc_curchan; /* current h/w channel */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t asc_rixmap[256]; /* IEEE to h/w rate table ix */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT asc_imask; /* interrupt mask copy */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_stats asc_stats; /* interface statistics */
3caf11144eab1a56717f986d44ae7f40ee8b28fcxc boolean_t asc_promisc; /* Promiscuous mode enabled */
3caf11144eab1a56717f986d44ae7f40ee8b28fcxc uint8_t asc_mcast_refs[ATH_MCHASH]; /* refer count */
3caf11144eab1a56717f986d44ae7f40ee8b28fcxc uint32_t asc_mcast_hash[2]; /* multicast hash table */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc kmutex_t asc_genlock;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc boolean_t asc_resched_needed;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc kmutex_t asc_resched_lock;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
a399b7655a1d835aa8606c2b29e4e777baac8635zf uint32_t asc_keymax; /* size of key cache */
a399b7655a1d835aa8606c2b29e4e777baac8635zf uint8_t asc_keymap[16]; /* bit map of key cache use */
a399b7655a1d835aa8606c2b29e4e777baac8635zf
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc timeout_id_t asc_scan_timer;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int (*asc_newstate)(ieee80211com_t *,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc enum ieee80211_state, int);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} ath_t;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_STATE(macinfo) ((ath_t *)((macinfo)->gldm_private))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_LOCK(_asc) mutex_enter(&(_asc)->asc_genlock)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_UNLOCK(_asc) mutex_exit(&(_asc)->asc_genlock)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_LOCK_ASSERT(_asc) ASSERT(mutex_owned(&(_asc)->asc_genlock))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
f11a3086bc0b6b242d387296efedd61d43316e8dxc#define ATH_IS_RUNNING(_asc) \
f11a3086bc0b6b242d387296efedd61d43316e8dxc (((_asc)->asc_invalid == 0) && ((_asc)->asc_isrunning == 1))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* Debug and log functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcvoid ath_dbg(uint32_t dbg_flags, const char *fmt, ...); /* debug function */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcvoid ath_log(const char *fmt, ...); /* event log function */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcvoid ath_problem(const char *fmt, ...); /* run-time problem function */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifdef __cplusplus
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc}
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif /* _ATH_IMPL_H */