3caf11144eab1a56717f986d44ae7f40ee8b28fcxc * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Use is subject to license terms.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * All rights reserved.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Redistribution and use in source and binary forms, with or without
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * modification, are permitted provided that the following conditions
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * are met:
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 1. Redistributions of source code must retain the above copyright
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * notice, this list of conditions and the following disclaimer,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * without modification.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 2. Redistributions in binary form must reproduce at minimum a disclaimer
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * redistribution must be conditioned upon including a substantially
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * similar Disclaimer requirement for further binary redistribution.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 3. Neither the names of the above-listed copyright holders nor the names
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * of any contributors may be used to endorse or promote products derived
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * from this software without specific prior written permission.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NO WARRANTY
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ath_impl.h is a bridge between the HAL and the driver. It
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * defines some data structures encapsulating the HAL interface
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * and communicating with the IEEE80211 MAC layer and other
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * driver components.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern "C" {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Defintions for the Atheros Wireless LAN controller driver.
a399b7655a1d835aa8606c2b29e4e777baac8635zf/* Bit map related macros. */
a399b7655a1d835aa8606c2b29e4e777baac8635zf#define clrbit(a, i) ((a)[(i)/NBBY] &= ~(1 << ((i)%NBBY)))
a399b7655a1d835aa8606c2b29e4e777baac8635zf#define isclr(a, i) (!((a)[(i)/NBBY] & (1 << ((i)%NBBY))))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Bit flags in the ath_dbg_flags
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DBG_80211 0x00000040 /* 80211 state machine */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc } while (0)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif /* DEBUG */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Node type of wifi device
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXQ_SETUP(asc, i) ((asc)->asc_txqsetup & (1<<i))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Sync a DMA area described by a dma_area_t
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXDESC 1 /* number of descriptors per buffer */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
1f156c6a7686102f9a1057cb9294c57041f3da68xc#define ATH_DEF_CACHE_BYTES 32 /* default cache line size */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* driver-specific node state */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t an_tx_antenna; /* antenna for last good frame */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_mgtratesp; /* short preamble h/w rate for " " */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate0sp; /* series 0 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate1sp; /* series 1 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate2sp; /* series 2 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t an_tx_rate3sp; /* series 3 short preamble h/w rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_hardware; /* fatal hardware error interrupts */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_mgmt; /* management frames transmitted */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_discard; /* frames discarded prior to assoc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_invalid; /* frames discarded 'cuz device gone */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_nobuf; /* tx failed 'cuz no tx buffer (data) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_nobufmgt; /* tx failed 'cuz no tx buffer(mgmt) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_xretries; /* tx failed 'cuz too many retries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_filtered; /* tx failed 'cuz xmit filtered */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_shortretry; /* tx on-chip retries (short) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_longretry; /* tx on-chip retries (long) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_noack; /* tx frames with no ack marked */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_shortpre; /* tx frames with short preamble */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_tx_altrate; /* tx frames with alternate rate */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ast_tx_protect; /* tx frames with protection */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_badcrypt; /* rx failed 'cuz decryption */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_phy[32]; /* rx PHY error per-code counts */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rx_tooshort; /* rx discarded 'cuz frame too short */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_per_calfail; /* periodic calibration failed */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_per_rfgain; /* periodic calibration rfgain reset */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rate_raise; /* rate control raised xmit rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ast_rate_drop; /* rate control dropped xmit rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Describes one chunk of allocated DMA-able memory
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * In some cases, this is a single chunk as allocated from the system;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * but we also use this structure to represent slices carved off such
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * a chunk. Even when we don't really need all the information, we
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * use this structure as a convenient way of correlating the various
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ways of looking at a piece of memory (kernel VA, IO space DVMA,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * handle+offset, etc).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* >= product of above */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc}; /* 0x50 (80) bytes */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China struct ath_desc_status bf_status; /* tx/rx status */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China mblk_t *bf_m; /* message for buf */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* we're in list of asc->asc_txbuf_list or asc->asc_rxbuf_list */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Data transmit queue state. One of these exists for each
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * hardware transmit queue. Packets sent to us from above
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * are assigned to queues based on their priority. Not all
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * devices support a complete set of hardware transmit queues.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * For those devices the array sc_ac2q will map multiple
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * priorities to fewer hardware queues (typically all to one
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * hardware queue).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * asc_isc must be the first element, for convience of
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * casting between iee80211com and ath
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China ddi_taskq_t *asc_tq; /* private task queue */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_RATE_TABLE *asc_rates[IEEE80211_MODE_MAX]; /* h/w rate */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t asc_protrix; /* protect rate index */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t asc_mcastantenna; /* Multicast antenna number */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* pointer to the first "struct ath_buf" */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* length of all allocated "struct ath_buf" */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* size of one DMA TX/RX buffer based on 802.11 MTU */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint64_t asc_lastrx; /* tsf at last rx'd frame */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_txq asc_txq[HAL_NUM_TX_QUEUES]; /* tx queues */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_RATE_TABLE *asc_currates; /* current rate table */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc enum ieee80211_phymode asc_curmode; /* current phy mode */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_STATE(macinfo) ((ath_t *)((macinfo)->gldm_private))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_LOCK_ASSERT(_asc) ASSERT(mutex_owned(&(_asc)->asc_genlock))
f11a3086bc0b6b242d387296efedd61d43316e8dxc (((_asc)->asc_invalid == 0) && ((_asc)->asc_isrunning == 1))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* Debug and log functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcvoid ath_dbg(uint32_t dbg_flags, const char *fmt, ...); /* debug function */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcvoid ath_log(const char *fmt, ...); /* event log function */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcvoid ath_problem(const char *fmt, ...); /* run-time problem function */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif /* _ATH_IMPL_H */