ath_hal.h revision 0ba2cbe97e0678a691742f98d2532caed0a2c4aa
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Communications, Inc. All rights reserved.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Use is subject to license terms.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Redistribution and use in source and binary forms are permitted
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * provided that the following conditions are met:
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 1. The materials contained herein are unmodified and are used
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * unmodified.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 2. Redistributions of source code must retain the above copyright
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * notice, this list of conditions and the following NO
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ''WARRANTY'' disclaimer below (''Disclaimer''), without
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * modification.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 3. Redistributions in binary form must reproduce at minimum a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * disclaimer similar to the Disclaimer below and any redistribution
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * must be conditioned upon including a substantially similar
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Disclaimer requirement for further binary redistribution.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 4. Neither the names of the above-listed copyright holders nor the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * names of any contributors may be used to endorse or promote
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * product derived from this software without specific prior written
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * permission.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NO WARRANTY
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * SUCH DAMAGES.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#pragma ident "%Z%%M% %I% %E% SMI"
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ath_hal.h is released by Atheros and used to describe the Atheros
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Hardware Access Layer(HAL) interface. All kinds of data structures,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * constant definition, APIs declaration are defined here.Clients of
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the HAL call ath_hal_attach() to obtain a reference to an ath_hal
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * structure for use with the device. Hardware-related operations that
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * follow must call back into the HAL through interface, supplying the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * reference as the first parameter.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern "C" {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* HAL version of this release */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* HAL data type definition */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxctypedef void * HAL_SOFTC; /* pointer to driver/OS state */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxctypedef void * HAL_BUS_HANDLE; /* opaque bus i/o handle */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_NUM_TX_QUEUES 10 /* max number of tx queues */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_RAD_INT 0x0001 /* Radar interference detected on channel */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_BUSY 0x0004 /* Busy, occupied or overlap with adjoin chan */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ|CHANNEL_TURBO)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_COMPAT (CHANNEL_ALL_NOTURBO | CHANNEL_PASSIVE)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/* privFlags */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Software use: channel interference used for AR as well as RADAR
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * interference detection
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked DFS */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* flags passed to tx descriptor setup methods */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/* NB: this only affects frame, not any RTS/CTS */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* flags passed to rx descriptor setup methods */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* tx error flags */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* rx error flags */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* value found in rs_keyix to mark invalid entries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* value used to specify no encryption key for xmit */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/* compression definitions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Status codes that may be returned by the HAL. Note that
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * interfaces that return a status code set it only when an
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * error occurs--i.e. you cannot check it for success.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc AH_FALSE = 0, /* NB: lots of code assumes false is zero */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* support */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_BURST = 13, /* hardware supports packet bursting */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* hardware can support TKIP MIC when WMM is turned on */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* hardware can support half rate channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* hardware can support quarter rate channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * "States" for setting the LED. These correspond to
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the possible 802.11 operational states and there may
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * be a many-to-one mapping between these states and the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * actual hardware states for the LED's (i.e. the hardware
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * may have fewer states).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit queue types/numbers. These are used to tag
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * each transmit queue in the hardware and to identify a set
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * of transmit queues for operations such as start/stop dma.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit queue subtype. These map directly to
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * WME Access Categories (except for UPSD). Refer
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to Table 5 of the WME spec.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit queue flags that control various
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * operational parameters.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Per queue interrupt enables. When set the associated
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * interrupt may be delivered for packets sent through
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the queue. Without these enabled no interrupts will
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * be delivered for transmits through the queue.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * When 0x0001 is set, both TXQ_TXOKINT and TXQ_TXERRINT
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * will be enabled.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Enable hardware compression for packets sent through
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the queue. The compression buffer must be setup and
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * packets must have a key entry marked in the tx descriptor.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Disable queue when veol is hit or ready time expires.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * By default the queue is disabled only on reaching the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * physical end of queue (i.e. a null link ptr in the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * descriptor chain).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Schedule frames on delivery of a DBA (DMA Beacon Alert)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * event. Frames will be transmitted only when this timer
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * fires, e.g to transmit a beacon in ap or adhoc modes.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Each transmit queue has a counter that is incremented
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * each time the queue is enabled and decremented when
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the list of frames to transmit is traversed (or when
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the ready time for the queue expires). This counter
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * must be non-zero for frames to be scheduled for
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * transmission. The following controls disable bumping
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * this counter under certain conditions. Typically this
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * is used to gate frames based on the contents of another
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * queue (e.g. CAB traffic may only follow a beacon frame).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * These are meaningful only when frames are scheduled
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * with a non-ASAP policy (e.g. DBA-gated).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Fragment burst backoff policy. Normally no backoff
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * is done after a successful transmission, the next fragment
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * is sent at SIFS. If this flag is set backoff is done
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * after each fragment, regardless whether it was ack'd or
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * not, after the backoff count reaches zero a normal channel
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * access procedure is done before the next transmit (i.e.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * wait AIFS instead of SIFS).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Disable post-tx backoff following each frame.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * DCU arbiter lockout control. This controls how
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * lower priority tx queues are handled with respect
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * to a specific queue when multiple queues have frames
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * to send. No lockout means lower priority queues arbitrate
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * concurrently with this queue. Intra-frame lockout
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * means lower priority queues are locked out until the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * current frame transmits (e.g. including backoffs and bursting).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Global lockout means nothing lower can arbitrary so
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * long as there is traffic activity on this queue (frames,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * backoff, etc).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_SEQNUM_INC_DIS = 0x00100000 /* disable seqnum increment */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* token to use for aifs, cwmin, cwmax */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit packet types. This belongs in ah_desc.h, but
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * is here so we can give a proper type to various parameters
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * (and not require everyone include the file).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NB: These values are intentionally assigned for
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * direct use when setting up h/w descriptors.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* Rx Filter Frame Types */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_PHYRADAR = 0x00000200 /* Allow phy radar errors */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NOTE WELL:
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * These are mapped to take advantage of the common locations for many of
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the bits on all of the currently supported MAC chips. This is to make
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the ISR as efficient as possible, while still abstracting HW differences.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * When new hardware breaks this commonality this enumerated type, as well
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * as the HAL functions using it, must be modified. All values are directly
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * mapped unless commented otherwise.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Interrupt bits that map directly to ISR/IMR bits */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* NB: these are specific to the 5212 */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Channels are specified by frequency.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int8_t maxRegTxPower; /* max regulatory tx power in dBm */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* mask for enabling short preamble in CCK rate code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* value for supported rates info element of MLME */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* index of next lower basic rate; used for dur. calcs */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t spAckDuration; /* short preamble ACK duration */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Antenna switch control. By default antenna selection
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * enables multiple (2) antenna use. To force use of the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * A or B antenna only specify a fixed setting. Fixing
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the antenna will also disable any diversity support.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Per-station beacon timer state. Note that the specified
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * beacon interval (given in TU's) can also include flags
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to force a TSF reset and to enable the beacon xmit logic.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * If bs_cfpmaxduration is non-zero the hardware is setup to
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * coexist with a PCF-capable AP.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Like HAL_BEACON_STATE but for non-station mode setup.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * NB: see above flag definitions
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Per-node statistics maintained by the driver for use in
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * optimizing signal quality and other operational aspects.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit descriptor status. This structure is filled
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * in only after the tx descriptor process method finds a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ``done'' descriptor; at which point it returns something
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * other than HAL_EINPROGRESS.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Note that ts_antenna may not be valid for all h/w. It
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * should be used only if non-zero.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Receive descriptor status. This structure is filled
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * in only after the rx descriptor process method finds a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ``done'' descriptor; at which point it returns something
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * other than HAL_EINPROGRESS.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * If rx_status is zero, then the frame was received ok;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * otherwise the error information is indicated and rs_phyerr
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * contains a phy error code if HAL_RXERR_PHY is set. In general
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the frame contents is undefined when an error occurred thought
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * for some errors (e.g. a decryption error), it may be meaningful.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Note that the receive timestamp is expanded using the TSF to
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * a full 16 bits (regardless of what the h/w provides directly).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * rx_rssi is in units of dbm above the noise floor. This value
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * is measured during the preamble and PLCP; i.e. with the initial
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 4us of detection. The noise floor is typically a consistent
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * -96dBm absolute power in a 20MHz channel.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Definitions for the software frame/packet descriptors used by
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the Atheros HAL. This definition obscures hardware-specific
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * details from the driver. Drivers are expected to fillin the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * portions of a descriptor that are not opaque then use HAL calls
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to complete the work. Status for completed frames is returned
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * in a device-independent format.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * The following definitions are passed directly
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the hardware and managed by the HAL. Drivers
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * should not touch those elements marked opaque.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * The remaining definitions are managed by software;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * these are valid only after the rx/tx process descriptor
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * methods return a non-EINPROGRESS code.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Hardware Access Layer (HAL) API.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Clients of the HAL call ath_hal_attach to obtain a reference to an
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ath_hal structure for use with the device. Hardware-related operations
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * that follow must call back into the HAL through interface, supplying
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the reference as the first parameter. Note that before using the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * reference returned by ath_hal_attach the caller should verify the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ABI version number.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* NB: when only one radio is present the rev is in 5Ghz */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* decomp mask array */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Reset functions */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_perCalibration) (struct ath_hal *, HAL_CHANNEL *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_processDfs)(struct ath_hal *, HAL_CHANNEL *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t (*ah_dfsNolCheck)(struct ath_hal *, HAL_CHANNEL *, uint32_t);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Transmit functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_releaseTxQueue) (struct ath_hal *ah, uint32_t q);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_resetTxQueue) (struct ath_hal *ah, uint32_t q);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setTxDP) (struct ath_hal *, uint32_t, uint32_t txdp);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_numTxPending)(struct ath_hal *, uint32_t q);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setupTxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setupXTxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_fillTxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_STATUS (*ah_procTxDesc) (struct ath_hal *, struct ath_desc *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc void (*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Receive Functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setMulticastFilterIndex) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_clrMulticastFilterIndex) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setupRxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_STATUS (*ah_procRxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Misc Functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_getDiagState) (struct ath_hal *, int request,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setMacAddress) (struct ath_hal *, const uint8_t *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setBssIdMask)(struct ath_hal *, const uint8_t *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_setLedState) (struct ath_hal *, HAL_LED_STATE);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_gpioCfgOutput) (struct ath_hal *, uint32_t gpio);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_gpioCfgInput) (struct ath_hal *, uint32_t gpio);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_gpioGet) (struct ath_hal *, uint32_t gpio);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_gpioSetIntr) (struct ath_hal *, uint32_t, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_updateMibCounters) (struct ath_hal *, HAL_MIB_STATS *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_ANT_SETTING (*ah_getAntennaSwitch) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setAntennaSwitch) (struct ath_hal *, HAL_ANT_SETTING);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setAckTimeout) (struct ath_hal *, uint32_t);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setAckCTSRate) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setCTSTimeout) (struct ath_hal *, uint32_t);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setDecompMask)(struct ath_hal *, uint16_t, int);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc void (*ah_setCoverageClass)(struct ath_hal *, uint8_t, int);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Key Cache Functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_resetKeyCacheEntry) (struct ath_hal *, uint16_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_isKeyCacheEntryValid) (struct ath_hal *, uint16_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const uint8_t *, int);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Power Management Functions */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int16_t (*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Beacon Management Functions */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* NB: deprecated, use ah_setBeaconTimers instead */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Interrupt functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_getPendingInterrupts) (struct ath_hal *, HAL_INT *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Check the PCI vendor ID and device ID against Atheros' values
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * and return a printable description for any Atheros hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * AH_NULL is returned if the ID's do not describe Atheros hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern const char *ath_hal_probe(uint16_t vendorid, uint16_t devid);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Attach the HAL for use with the specified device. The device is
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * defined by the PCI device ID. The caller provides an opaque pointer
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to an upper-layer data structure (HAL_SOFTC) that is stored in the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * HAL state block for later use. Hardware register accesses are done
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * using the specified bus tag and handle. On successful return a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * reference to a state block is returned that must be supplied in all
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * subsequent HAL calls. Storage associated with this reference is
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * dynamically allocated and must be freed by calling the ah_detach
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * method when the client is done. If the attach operation fails a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * null (AH_NULL) reference will be returned and a status code will
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * be returned if the status parameter is non-zero.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern struct ath_hal *ath_hal_attach(uint16_t devid, HAL_SOFTC,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Set the Vendor ID for Vendor SKU's which can modify the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * channel properties returned by ath_hal_init_channels.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Return AH_TRUE if set succeeds
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern HAL_BOOL ath_hal_setvendor(struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return a list of channels available for use with the hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * The list is based on what the hardware is capable of, the specified
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * country code, the modeSelect mask, and whether or not outdoor
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * channels are to be permitted.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * The channel list is returned in the supplied array. maxchans
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * defines the maximum size of this array. nchans contains the actual
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * number of channels returned. If a problem occurred or there were
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * no channels that met the criteria then AH_FALSE is returned.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint8_t *regclassids, uint32_t maxregids, uint32_t *nregids,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Calibrate noise floor data following a channel scan or similar.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * This must be called prior retrieving noise floor data.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern void ath_hal_process_noisefloor(struct ath_hal *ah);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return bit mask of wireless modes supported by the hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern uint32_t ath_hal_getwirelessmodes(struct ath_hal *, HAL_CTRY_CODE);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return rate table for specified mode (11a, 11b, 11g, etc).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern const HAL_RATE_TABLE * ath_hal_getratetable(struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Calculate the transmit duration of a frame.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Return if device is public safety.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern HAL_BOOL ath_hal_ispublicsafetysku(struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Convert between IEEE channel number and channel frequency
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * using the specified channel flags; e.g. CHANNEL_2GHZ.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern int ath_hal_mhz2ieee(struct ath_hal *, uint32_t mhz, uint32_t flags);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return a version string for the HAL release.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern char ath_hal_version[];
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return a NULL-terminated array of build/configuration options.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern const char *ath_hal_buildopts[];
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Macros to encapsulated HAL functions.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_RESET(_ah, _opmode, _chan, _outdoor, _pstatus) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETCAPABILITY(_ah, _cap, _param, _result) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_SETCAPABILITY(_ah, _type, _cap, _param, _status) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*ah_setCapability)((_ah), (_type), (_cap), (_param), (_status)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_beacon_state)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETUPBEACONDESC(_ah, _ds, _opmode, _flen, _hlen, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETUPTXDESC(_ah, _ds, _plen, _hlen, _atype, _txpow, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_FILLTXDESC(_ah, _ds, _l, _first, _last, _ath_desc) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif /* _ATH_HAL_H */