7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Communications, Inc. All rights reserved.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Use is subject to license terms.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Redistribution and use in source and binary forms are permitted
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * provided that the following conditions are met:
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 1. The materials contained herein are unmodified and are used
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * unmodified.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 2. Redistributions of source code must retain the above copyright
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * notice, this list of conditions and the following NO
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ''WARRANTY'' disclaimer below (''Disclaimer''), without
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * modification.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 3. Redistributions in binary form must reproduce at minimum a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * disclaimer similar to the Disclaimer below and any redistribution
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * must be conditioned upon including a substantially similar
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Disclaimer requirement for further binary redistribution.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 4. Neither the names of the above-listed copyright holders nor the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * names of any contributors may be used to endorse or promote
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * product derived from this software without specific prior written
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * permission.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NO WARRANTY
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * SUCH DAMAGES.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifndef _ATH_HAL_H
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define _ATH_HAL_H
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ath_hal.h is released by Atheros and used to describe the Atheros
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Hardware Access Layer(HAL) interface. All kinds of data structures,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * constant definition, APIs declaration are defined here.Clients of
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the HAL call ath_hal_attach() to obtain a reference to an ath_hal
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * structure for use with the device. Hardware-related operations that
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * follow must call back into the HAL through interface, supplying the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * reference as the first parameter.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifdef __cplusplus
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern "C" {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* HAL version of this release */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_ABI_VERSION 0x08052700 /* YYMMDDnn */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* HAL data type definition */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxctypedef void * HAL_SOFTC; /* pointer to driver/OS state */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxctypedef void * HAL_BUS_TAG; /* opaque bus i/o id tag */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxctypedef void * HAL_BUS_HANDLE; /* opaque bus i/o handle */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef uint32_t HAL_BUS_ADDR;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef uint16_t HAL_CTRY_CODE; /* country code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_NUM_TX_QUEUES 10 /* max number of tx queues */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_RAD_INT 0x00001 /* Radar interference detected on channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_BUSY 0x00004 /* Busy, occupied or overlap with adjoin chan */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_TURBO 0x00010 /* Turbo Channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_CCK 0x00020 /* CCK channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_OFDM 0x00040 /* OFDM channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel. */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_XR 0x00800 /* XR channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_HALF 0x04000 /* Half rate channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ chan w/ ext chan above */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ chan w/ ext chan below */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_108A CHANNEL_T
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_G_HT40PLUS (CHANNEL_G_HT20|CHANNEL_HT40PLUS)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_A_HT40PLUS (CHANNEL_A_HT20|CHANNEL_HT40PLUS)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define CHANNEL_A_HT40MINUS (CHANNEL_A_HT20|CHANNEL_HT40MINUS)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_ALL \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ| \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China CHANNEL_TURBO|CHANNEL_HT20|CHANNEL_HT40PLUS|CHANNEL_HT40MINUS)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_COMPAT (CHANNEL_ALL_NOTURBO | CHANNEL_PASSIVE)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/* privFlags */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Software use: channel interference used for AR as well as RADAR
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * interference detection
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_INTERFERENCE 0x01
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_DFS 0x02 /* DFS required on channel */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked DFS */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* flags passed to tx descriptor setup methods */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/* NB: this only affects frame, not any RTS/CTS */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TXDESC_VMF 0x0200 /* virtual more frag */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* flags passed to rx descriptor setup methods */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* tx error flags */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXERR_XRETRY 0x01 /* excessive retries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXERR_FIFO 0x04 /* fifo underrun */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TXERR_XTXOP 0x08 /* txop exceeded */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TXERR_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TXERR_DATA_UNDERRUN 0x20 /* Tx buffer underrun */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TXERR_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China/* bits found in ts_flags */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TX_BA 0x01 /* Block Ack seen */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_TX_AGGR 0x02 /* Aggregate */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* rx error flags */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_CRC 0x01 /* CRC error on frame */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_FIFO 0x04 /* fifo overrun */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China/* bits found in rs_flags */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_MORE 0x01 /* more descriptors follow */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_GI 0x04 /* full gi */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_2040 0x08 /* 40 Mhz */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RX_DUP_FRAME 0x80 /* Dup frame rx'd on control channel */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* value found in rs_keyix to mark invalid entries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_RXKEYIX_INVALID ((uint8_t)-1)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* value used to specify no encryption key for xmit */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXKEYIX_INVALID ((uint32_t)-1)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/* compression definitions */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9k */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_COMP_BUF_ALIGN_SIZE 512
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_ANTENNA_MIN_MODE 0
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_ANTENNA_FIXED_A 1
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_ANTENNA_FIXED_B 2
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_ANTENNA_MAX_MODE 3
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Status codes that may be returned by the HAL. Note that
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * interfaces that return a status code set it only when an
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * error occurs--i.e. you cannot check it for success.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_OK = 0, /* No error */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_ENXIO = 1, /* No hardware present */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_ENOMEM = 2, /* Memory allocation failed */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EIO = 3, /* Hardware didn't respond as expected */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EEVERSION = 5, /* EEPROM version invalid */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EELOCKED = 6, /* EEPROM unreadable */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EEREAD = 8, /* EEPROM read problem */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EESIZE = 10, /* EEPROM size not supported */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EINVAL = 12, /* Invalid parameter to function */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_ENOTSUPP = 13, /* Hardware revision not supported */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_ESELFTEST = 14, /* Hardware self-test failed */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_EINPROGRESS = 15 /* Operation incomplete */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_STATUS;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc AH_FALSE = 0, /* NB: lots of code assumes false is zero */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc AH_TRUE = 1
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_BOOL;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_REG_DMN = 0, /* current regulatory domain */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_CIPHER = 1, /* hardware supports cipher */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* support */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_DIAG = 11, /* hardware diagnostic support */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_BURST = 13, /* hardware supports packet bursting */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAP_TXPOW = 15, /* global tx power limit */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_TPC = 16, /* per-packet tx power control */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_XR = 21, /* hardware has XR support */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* hardware can support TKIP MIC when WMM is turned on */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_WME_TKIPMIC = 22,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* hardware can support half rate channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_CHAN_HALFRATE = 23,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* hardware can support quarter rate channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_CHAN_QUARTERRATE = 24,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CAP_INTMIT = 29, /* interference mitigation */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CAP_HT = 31, /* hardware can support HT */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CAP_NUMTXCHAIN = 32, /* TX chains supported */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CAP_NUMRXCHAIN = 33, /* RX chains supported */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CAP_RXTSTAMP_PREC = 34 /* rx desc tstamp precision (bits) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_CAPABILITY_TYPE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * "States" for setting the LED. These correspond to
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the possible 802.11 operational states and there may
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * be a many-to-one mapping between these states and the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * actual hardware states for the LED's (i.e. the hardware
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * may have fewer states).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_LED_INIT = 0,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_LED_SCAN = 1,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_LED_AUTH = 2,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_LED_ASSOC = 3,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_LED_RUN = 4
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_LED_STATE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit queue types/numbers. These are used to tag
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * each transmit queue in the hardware and to identify a set
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * of transmit queues for operations such as start/stop dma.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TX_QUEUE_UAPSD = 4 /* u-apsd power save xmit q */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_TX_QUEUE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit queue subtype. These map directly to
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * WME Access Categories (except for UPSD). Refer
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to Table 5 of the WME spec.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_WME_AC_BK = 0, /* background access category */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_WME_AC_BE = 1, /* best effort access category */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_WME_AC_VI = 2, /* video access category */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_WME_AC_VO = 3, /* voice access category */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_WME_UPSD = 4, /* uplink power save */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_XR_DATA = 5 /* entended range data */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_TX_QUEUE_SUBTYPE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit queue flags that control various
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * operational parameters.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Per queue interrupt enables. When set the associated
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * interrupt may be delivered for packets sent through
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the queue. Without these enabled no interrupts will
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * be delivered for transmits through the queue.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc *
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * When 0x0001 is set, both TXQ_TXOKINT and TXQ_TXERRINT
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * will be enabled.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Enable hardware compression for packets sent through
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the queue. The compression buffer must be setup and
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * packets must have a key entry marked in the tx descriptor.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Disable queue when veol is hit or ready time expires.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * By default the queue is disabled only on reaching the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * physical end of queue (i.e. a null link ptr in the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * descriptor chain).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Schedule frames on delivery of a DBA (DMA Beacon Alert)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * event. Frames will be transmitted only when this timer
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * fires, e.g to transmit a beacon in ap or adhoc modes.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Each transmit queue has a counter that is incremented
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * each time the queue is enabled and decremented when
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the list of frames to transmit is traversed (or when
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the ready time for the queue expires). This counter
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * must be non-zero for frames to be scheduled for
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * transmission. The following controls disable bumping
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * this counter under certain conditions. Typically this
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * is used to gate frames based on the contents of another
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * queue (e.g. CAB traffic may only follow a beacon frame).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * These are meaningful only when frames are scheduled
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * with a non-ASAP policy (e.g. DBA-gated).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Fragment burst backoff policy. Normally no backoff
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * is done after a successful transmission, the next fragment
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * is sent at SIFS. If this flag is set backoff is done
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * after each fragment, regardless whether it was ack'd or
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * not, after the backoff count reaches zero a normal channel
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * access procedure is done before the next transmit (i.e.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * wait AIFS instead of SIFS).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Disable post-tx backoff following each frame.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * DCU arbiter lockout control. This controls how
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * lower priority tx queues are handled with respect
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * to a specific queue when multiple queues have frames
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * to send. No lockout means lower priority queues arbitrate
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * concurrently with this queue. Intra-frame lockout
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * means lower priority queues are locked out until the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * current frame transmits (e.g. including backoffs and bursting).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Global lockout means nothing lower can arbitrary so
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * long as there is traffic activity on this queue (frames,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * backoff, etc).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_TXQ_SEQNUM_INC_DIS = 0x00100000 /* disable seqnum increment */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_TX_QUEUE_FLAGS;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t tqi_ver; /* hal TXQ version */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t tqi_priority; /* (not used) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t tqi_aifs; /* AIFS shift */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int32_t tqi_cwmin; /* cwMin shift */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int32_t tqi_cwmax; /* cwMax shift */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t tqi_shretry; /* rts retry limit */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t tqi_lgretry; /* long retry limit(not used) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t tqi_cbrPeriod;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t tqi_cbrOverflowLimit;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t tqi_burstTime;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t tqi_readyTime;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t tqi_compBuf; /* compress buffer phys addr */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_TXQ_INFO;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TQI_NONVAL 0xffff
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* token to use for aifs, cwmin, cwmax */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define HAL_TXQ_USEDEFAULT ((uint32_t)-1)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit packet types. This belongs in ah_desc.h, but
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * is here so we can give a proper type to various parameters
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * (and not require everyone include the file).
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NB: These values are intentionally assigned for
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * direct use when setting up h/w descriptors.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PKT_TYPE_NORMAL = 0,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PKT_TYPE_ATIM = 1,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PKT_TYPE_PSPOLL = 2,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PKT_TYPE_BEACON = 3,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_PKT_TYPE_PROBE_RESP = 4,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_PKT_TYPE_CHIRP = 5,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_PKT_TYPE_GRP_POLL = 6,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_PKT_TYPE_AMPDU = 7
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_PKT_TYPE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/* Rx Filter Frame Types */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RX_FILTER_PHYRADAR = 0x00000200 /* Allow phy radar errors */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_RX_FILTER;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_PM_AWAKE = 0,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_PM_FULL_SLEEP = 1,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_PM_NETWORK_SLEEP = 2,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_PM_UNDEFINED = 3
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_POWER_MODE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * NOTE WELL:
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * These are mapped to take advantage of the common locations for many of
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the bits on all of the currently supported MAC chips. This is to make
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the ISR as efficient as possible, while still abstracting HW differences.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * When new hardware breaks this commonality this enumerated type, as well
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * as the HAL functions using it, must be modified. All values are directly
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * mapped unless commented otherwise.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_RX = 0x00000001, /* Non-common mapping */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_RXDESC = 0x00000002,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_RXNOFRM = 0x00000008,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_RXEOL = 0x00000010,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_RXORN = 0x00000020,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_TX = 0x00000040, /* Non-common mapping */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_TXDESC = 0x00000080,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_TXURN = 0x00000800,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_MIB = 0x00001000,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_RXPHY = 0x00004000,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_RXKCM = 0x00008000,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_SWBA = 0x00010000,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_BMISS = 0x00040000,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_BNR = 0x00100000, /* Non-common mapping */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_INT_TIM = 0x00200000, /* Non-common mapping */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_INT_DTIMSYNC = 0x00800000, /* Non-common mapping */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_GPIO = 0x01000000,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_INT_CST = 0x10000000, /* Non-common mapping */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_INT_GTT = 0x20000000, /* Non-common mapping */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_GLOBAL = INT_MIN, /* Set/clear IER */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_INT_BMISC = HAL_INT_TIM
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc | HAL_INT_DTIM
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc | HAL_INT_DTIMSYNC
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc | HAL_INT_CABEND,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Interrupt bits that map directly to ISR/IMR bits */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT_COMMON = HAL_INT_RXNOFRM
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_RXDESC
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_RXEOL
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_RXORN
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_TXURN
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_TXDESC
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_MIB
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_RXPHY
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_RXKCM
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_SWBA
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_BMISS
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc | HAL_INT_GPIO,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_INT;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RFGAIN_INACTIVE = 0,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RFGAIN_READ_REQUESTED = 1,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RFGAIN_NEED_CHANGE = 2
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_RFGAIN;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_TIMING = 1, /* Timing error */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_PARITY = 2, /* Illegal parity */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_RATE = 3, /* Illegal rate */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_LENGTH = 4, /* Illegal length */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_RADAR = 5, /* Radar detect */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_SERVICE = 6, /* Illegal service */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_TOR = 7, /* Transmit override receive */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* NB: these are specific to the 5212 */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_OFDM_TIMING = 17, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_OFDM_SERVICE = 22, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_OFDM_RESTART = 23, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_CCK_TIMING = 25, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_CCK_SERVICE = 30, /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PHYERR_CCK_RESTART = 31 /* */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc}HAL_PHYERR;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Channels are specified by frequency.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t channelFlags;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t channel; /* setting in Mhz */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint8_t privFlags;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int8_t maxRegTxPower; /* max regulatory tx power in dBm */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int8_t maxTxPower; /* max true tx power in 0.5 dBm */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int8_t minTxPower; /* min true tx power in 0.5 dBm */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_CHANNEL;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ackrcv_bad;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t rts_bad;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t rts_good;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t fcs_bad;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t beacons;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_MIB_STATS;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcenum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc CTRY_DEBUG = 0x1ff, /* debug country code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc CTRY_DEFAULT = 0 /* default country code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcenum {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_11A = 0x001, /* 11a channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_11B = 0x004, /* 11b channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_11G = 0x008, /* XXX historical */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_XR = 0x100, /* XR channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_MODE_11NG_HT20 = 0x8000,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_MODE_11NA_HT20 = 0x10000,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_MODE_11NG_HT40PLUS = 0x20000,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_MODE_11NG_HT40MINUS = 0x40000,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_MODE_11NA_HT40PLUS = 0x80000,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_MODE_11NA_HT40MINUS = 0x100000,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_MODE_ALL = 0xffffff
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int rateCount; /* NB: for proper padding */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t rateCodeToIndex[144]; /* back mapping */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t valid; /* valid for rate control use */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t phy; /* CCK/OFDM/XR */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t rateKbps; /* transfer rate in kbs */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t rateCode; /* rate for h/w descriptors */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* mask for enabling short preamble in CCK rate code */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t shortPreamble;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* value for supported rates info element of MLME */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t dot11Rate;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* index of next lower basic rate; used for dur. calcs */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t controlRate;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t lpAckDuration; /* long preamble ACK duration */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t spAckDuration; /* short preamble ACK duration */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc } info[32];
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_RATE_TABLE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t rs_count; /* number of valid entries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t rs_rates[32]; /* rates */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_RATE_SET;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China/*
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China * 802.11n specific structures and enums
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinatypedef enum {
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CHAINTYPE_TX = 1, /* Tx chain type */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CHAINTYPE_RX = 2, /* RX chain type */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China} HAL_CHAIN_TYPE;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinatypedef struct {
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint_t Tries;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint_t Rate;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint_t PktDuration;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint_t ChSel;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint_t RateFlags;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China} HAL_11N_RATE_SERIES;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinatypedef enum {
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_HT_MACMODE_2040 = 1 /* 20/40 MHz operation */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China} HAL_HT_MACMODE;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinatypedef enum {
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_HT_PHYMODE_2040 = 1 /* 20/40 MHz operation */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China} HAL_HT_PHYMODE;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinatypedef enum {
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_HT_EXTPROTSPACING_25 = 1 /* 25 MHz spacing */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China} HAL_HT_EXTPROTSPACING;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinatypedef enum {
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_RX_CLEAR_CTL_LOW = 1, /* force control chan to appear busy */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_RX_CLEAR_EXT_LOW = 2 /* force ext chan to appear busy */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China} HAL_HT_RXCLEAR;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Antenna switch control. By default antenna selection
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * enables multiple (2) antenna use. To force use of the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * A or B antenna only specify a fixed setting. Fixing
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * the antenna will also disable any diversity support.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_ANT_VARIABLE = 0, /* variable by programming */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_ANT_FIXED_A = 1, /* fixed antenna A */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_ANT_FIXED_B = 2 /* fixed antenna B */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_ANT_SETTING;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_M_STA = 1, /* infrastructure station */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_M_IBSS = 0, /* IBSS (adhoc) station */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_M_HOSTAP = 6, /* Software Access Point */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_M_MONITOR = 8 /* Monitor mode */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_OPMODE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t kv_type; /* one of HAL_CIPHER */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t kv_pad;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t kv_len; /* length in bits */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t kv_val[16]; /* enough for 128-bit keys */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t kv_mic[8]; /* TKIP MIC key */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_KEYVAL;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef enum {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CIPHER_WEP = 0,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CIPHER_AES_OCB = 1,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CIPHER_AES_CCM = 2,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CIPHER_CKIP = 3,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CIPHER_TKIP = 4,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CIPHER_CLR = 5, /* no encryption */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_CIPHER;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcenum {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_SLOT_TIME_9 = 9,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_SLOT_TIME_20 = 20
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Per-station beacon timer state. Note that the specified
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * beacon interval (given in TU's) can also include flags
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to force a TSF reset and to enable the beacon xmit logic.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * If bs_cfpmaxduration is non-zero the hardware is setup to
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * coexist with a PCF-capable AP.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t bs_nexttbtt; /* next beacon in TU */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t bs_nextdtim; /* next DTIM in TU */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t bs_intval; /* beacon interval+flags */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t bs_dtimperiod;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t bs_cfpperiod; /* CFP period in TU */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t bs_cfpnext; /* next CFP in TU */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t bs_timoffset; /* byte offset to TIM bitmap */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t bs_bmissthreshold; /* beacon miss threshold */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t bs_sleepduration; /* max sleep duration */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_BEACON_STATE;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Like HAL_BEACON_STATE but for non-station mode setup.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * NB: see above flag definitions
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxctypedef struct {
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t bt_intval; /* beacon interval+flags */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t bt_nexttbtt; /* next beacon in TU */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t bt_nextatim; /* next ATIM in TU */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t bt_nextdba; /* next DBA in 1/8th TU */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t bt_flags; /* timer enables */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_BEACON_TBTT_EN 0x00000001
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_BEACON_DBA_EN 0x00000002
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_BEACON_SWBA_EN 0x00000004
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc} HAL_BEACON_TIMERS;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Per-node statistics maintained by the driver for use in
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * optimizing signal quality and other operational aspects.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xctypedef struct {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ns_avgbrssi; /* average beacon rssi */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ns_avgrssi; /* average data rssi */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ns_avgtxrssi; /* average tx rssi */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc} HAL_NODE_STATS;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Transmit descriptor status. This structure is filled
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * in only after the tx descriptor process method finds a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ``done'' descriptor; at which point it returns something
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * other than HAL_EINPROGRESS.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Note that ts_antenna may not be valid for all h/w. It
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * should be used only if non-zero.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_tx_status {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t ts_seqnum; /* h/w assigned sequence number */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t ts_tstamp; /* h/w assigned timestamp */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t ts_status; /* frame status, 0 => xmit ok */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t ts_rate; /* h/w transmit rate index */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int8_t ts_rssi; /* tx ack RSSI */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t ts_shortretry; /* # short retries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t ts_longretry; /* # long retries */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t ts_virtcol; /* virtual collision count */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t ts_antenna; /* antenna information */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t ts_finaltsi; /* final transmit series index */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China /* AH_SUPPORT_AR5416 */ /* 802.11n status */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t ts_flags; /* misc flags */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ts_ba_low; /* blockack bitmap low */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ts_ba_high; /* blockack bitmap high */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ts_evm0; /* evm bytes */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ts_evm1;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ts_evm2;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Receive descriptor status. This structure is filled
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * in only after the rx descriptor process method finds a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ``done'' descriptor; at which point it returns something
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * other than HAL_EINPROGRESS.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * If rx_status is zero, then the frame was received ok;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * otherwise the error information is indicated and rs_phyerr
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * contains a phy error code if HAL_RXERR_PHY is set. In general
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the frame contents is undefined when an error occurred thought
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * for some errors (e.g. a decryption error), it may be meaningful.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Note that the receive timestamp is expanded using the TSF to
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China * at least 15 bits (regardless of what the h/w provides directly).
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China * find out if the hardware is capable.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * rx_rssi is in units of dbm above the noise floor. This value
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * is measured during the preamble and PLCP; i.e. with the initial
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * 4us of detection. The noise floor is typically a consistent
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * -96dBm absolute power in a 20MHz channel.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_rx_status {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t rs_datalen; /* rx frame length */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t rs_status; /* rx status, 0 => recv ok */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t rs_phyerr; /* phy error code */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China int8_t rs_rssi; /* rx frame RSSI (xombined for 11n) */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t rs_keyix; /* key cache index */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t rs_rate; /* h/w receive rate index */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint8_t rs_more; /* see HAL_RXERR_XXX definition */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t rs_tstamp; /* h/w assigned timestamp */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t rs_antenna; /* antenna information */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China /* AH_SUPPORT_AR5416 */ /* 802.11n status */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t rs_isaggr; /* is part of the aggregate */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t rs_moreaggr; /* more frames in aggr to follow */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t rs_num_delims; /* number of delims in aggr */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint8_t rs_flags; /* misc flags */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t rs_evm0; /* evm bytes */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t rs_evm1;
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t rs_evm2;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Definitions for the software frame/packet descriptors used by
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the Atheros HAL. This definition obscures hardware-specific
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * details from the driver. Drivers are expected to fillin the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * portions of a descriptor that are not opaque then use HAL calls
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to complete the work. Status for completed frames is returned
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * in a device-independent format.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China/* AH_SUPPORT_AR5416 */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define HAL_DESC_HW_SIZE 20
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#pragma pack(1)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_desc {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * The following definitions are passed directly
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the hardware and managed by the HAL. Drivers
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * should not touch those elements marked opaque.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ds_link; /* phys address of next descriptor */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ds_data; /* phys address of data buffer */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ds_ctl0; /* opaque DMA control 0 */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ds_ctl1; /* opaque DMA control 1 */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China};
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinastruct ath_desc_status {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc union {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_tx_status tx; /* xmit status */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc struct ath_rx_status rx; /* recv status */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc } ds_us;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#pragma pack()
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ds_txstat ds_us.tx
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ds_rxstat ds_us.rx
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Hardware Access Layer (HAL) API.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Clients of the HAL call ath_hal_attach to obtain a reference to an
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ath_hal structure for use with the device. Hardware-related operations
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * that follow must call back into the HAL through interface, supplying
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * the reference as the first parameter. Note that before using the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * reference returned by ath_hal_attach the caller should verify the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * ABI version number.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcstruct ath_hal {
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ah_magic; /* consistency check magic number */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ah_abi; /* HAL ABI version */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t ah_devid; /* PCI device ID */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t ah_subvendorid; /* PCI subvendor ID */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_SOFTC ah_sc; /* back pointer to driver/os state */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BUS_TAG ah_st; /* params for register r+w */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BUS_HANDLE ah_sh;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CTRY_CODE ah_countryCode;
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t ah_macVersion; /* MAC version id */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t ah_macRev; /* MAC revision */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t ah_phyRev; /* PHY revision */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* NB: when only one radio is present the rev is in 5Ghz */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint16_t ah_analog5GhzRev; /* 5GHz radio revision */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint16_t ah_analog2GhzRev; /* 2GHz radio revision */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t mode);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_detach) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Reset functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_reset) (struct ath_hal *, HAL_OPMODE,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CHANNEL *, HAL_BOOL bChannelChange,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_STATUS *status);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_phyDisable) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_disable) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc void (*ah_setPCUConfig) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_perCalibration) (struct ath_hal *, HAL_CHANNEL *,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China /* DFS support */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Transmit functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_updateTxTrigLevel) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL incTrigLevel);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc int (*ah_setupTxQueue) (struct ath_hal *, HAL_TX_QUEUE,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_TXQ_INFO *qInfo);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setTxQueueProps) (struct ath_hal *, int q,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_TXQ_INFO *qInfo);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_getTxQueueProps)(struct ath_hal *, int q,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_TXQ_INFO *qInfo);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_releaseTxQueue) (struct ath_hal *ah, uint32_t q);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_resetTxQueue) (struct ath_hal *ah, uint32_t q);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getTxDP) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setTxDP) (struct ath_hal *, uint32_t, uint32_t txdp);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_numTxPending)(struct ath_hal *, uint32_t q);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_startTxDma) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_stopTxDma) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setupTxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t pktLen, uint32_t hdrLen,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_PKT_TYPE type, uint32_t txPower,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t txRate0, uint32_t txTries0,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t keyIx, uint32_t antMode,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t flags, uint32_t rtsctsRate,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t rtsctsDuration,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t compicvLen, uint32_t compivLen,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t comp);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setupXTxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t txRate1, uint32_t txTries1,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t txRate2, uint32_t txTries2,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t txRate3, uint32_t txTries3);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_fillTxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t segLen, HAL_BOOL firstSeg,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL lastSeg, const struct ath_desc *);
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_STATUS (*ah_procTxDesc)(struct ath_hal *, struct ath_desc *,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China struct ath_tx_status *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc void (*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Receive Functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getRxDP) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_setRxDP) (struct ath_hal *, uint32_t rxdp);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_enableReceive) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_stopDmaReceive) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_startPcuReceive) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_stopPcuReceive) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_setMulticastFilter) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t filter0, uint32_t filter1);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setMulticastFilterIndex) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t index);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_clrMulticastFilterIndex) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t index);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getRxFilter) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_setRxFilter) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setupRxDesc) (struct ath_hal *, struct ath_desc *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t size, uint32_t flags);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_STATUS (*ah_procRxDesc) (struct ath_hal *, struct ath_desc *,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t phyAddr, struct ath_desc *next,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint64_t tsf, struct ath_rx_status *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_rxMonitor) (struct ath_hal *,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc const HAL_NODE_STATS *, HAL_CHANNEL *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_procMibEvent) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_NODE_STATS *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Misc Functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_STATUS (*ah_getCapability) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAPABILITY_TYPE, uint32_t capability,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t *result);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setCapability) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CAPABILITY_TYPE, uint32_t capability,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t setting, HAL_STATUS *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_getDiagState) (struct ath_hal *, int request,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const void *args, uint32_t argsize,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void **result, uint32_t *resultsize);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_getMacAddress) (struct ath_hal *, uint8_t *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setMacAddress) (struct ath_hal *, const uint8_t *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc void (*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setBssIdMask)(struct ath_hal *, const uint8_t *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setRegulatoryDomain) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t, HAL_STATUS *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_setLedState) (struct ath_hal *, HAL_LED_STATE);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_writeAssocid) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const uint8_t *bssid, uint16_t assocId);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_gpioCfgOutput) (struct ath_hal *, uint32_t gpio);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_gpioCfgInput) (struct ath_hal *, uint32_t gpio);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_gpioGet) (struct ath_hal *, uint32_t gpio);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_gpioSet) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t gpio, uint32_t val);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_gpioSetIntr) (struct ath_hal *, uint32_t, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getTsf32) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint64_t (*ah_getTsf64) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_resetTsf) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_detectCardPresent) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_updateMibCounters) (struct ath_hal *, HAL_MIB_STATS *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_RFGAIN (*ah_getRfGain) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getDefAntenna) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_setDefAntenna) (struct ath_hal *, uint32_t);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_ANT_SETTING (*ah_getAntennaSwitch) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setAntennaSwitch) (struct ath_hal *, HAL_ANT_SETTING);
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_BOOL (*ah_setSifsTime) (struct ath_hal *, uint32_t);
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China uint32_t (*ah_getSifsTime) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setSlotTime) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getSlotTime) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setAckTimeout) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getAckTimeout) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setAckCTSRate) (struct ath_hal *, uint32_t);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t (*ah_getAckCTSRate) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setCTSTimeout) (struct ath_hal *, uint32_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getCTSTimeout) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_BOOL (*ah_setDecompMask)(struct ath_hal *, uint16_t, int);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc void (*ah_setCoverageClass)(struct ath_hal *, uint8_t, int);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Key Cache Functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t (*ah_getKeyCacheSize) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_resetKeyCacheEntry) (struct ath_hal *, uint16_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_isKeyCacheEntryValid) (struct ath_hal *, uint16_t);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setKeyCacheEntry) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t, const HAL_KEYVAL *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const uint8_t *, int);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setKeyCacheEntryMac) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t, const uint8_t *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Power Management Functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_setPowerMode) (struct ath_hal *,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc HAL_POWER_MODE mode, int setChip);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_POWER_MODE (*ah_getPowerMode) (struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc int16_t (*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Beacon Management Functions */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc void (*ah_setBeaconTimers) (struct ath_hal *,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc const HAL_BEACON_TIMERS *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* NB: deprecated, use ah_setBeaconTimers instead */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_beaconInit) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint32_t nexttbtt, uint32_t intval);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_setStationBeaconTimers) (struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_BEACON_STATE *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc void (*ah_resetStationBeaconTimers) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc /* Interrupt functions */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_isInterruptPending) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL (*ah_getPendingInterrupts) (struct ath_hal *, HAL_INT *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT (*ah_getInterrupts) (struct ath_hal *);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_INT (*ah_setInterrupts) (struct ath_hal *, HAL_INT);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc};
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Check the PCI vendor ID and device ID against Atheros' values
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * and return a printable description for any Atheros hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * AH_NULL is returned if the ID's do not describe Atheros hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern const char *ath_hal_probe(uint16_t vendorid, uint16_t devid);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Attach the HAL for use with the specified device. The device is
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * defined by the PCI device ID. The caller provides an opaque pointer
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * to an upper-layer data structure (HAL_SOFTC) that is stored in the
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * HAL state block for later use. Hardware register accesses are done
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * using the specified bus tag and handle. On successful return a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * reference to a state block is returned that must be supplied in all
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * subsequent HAL calls. Storage associated with this reference is
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * dynamically allocated and must be freed by calling the ah_detach
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * method when the client is done. If the attach operation fails a
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * null (AH_NULL) reference will be returned and a status code will
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * be returned if the status parameter is non-zero.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern struct ath_hal *ath_hal_attach(uint16_t devid, HAL_SOFTC,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *status);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Set the Vendor ID for Vendor SKU's which can modify the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * channel properties returned by ath_hal_init_channels.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Return AH_TRUE if set succeeds
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern HAL_BOOL ath_hal_setvendor(struct ath_hal *, uint32_t);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return a list of channels available for use with the hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * The list is based on what the hardware is capable of, the specified
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * country code, the modeSelect mask, and whether or not outdoor
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * channels are to be permitted.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc *
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * The channel list is returned in the supplied array. maxchans
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * defines the maximum size of this array. nchans contains the actual
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * number of channels returned. If a problem occurred or there were
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * no channels that met the criteria then AH_FALSE is returned.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern HAL_BOOL ath_hal_init_channels(struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_CHANNEL *chans, uint32_t maxchans, uint32_t *nchans,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint8_t *regclassids, uint32_t maxregids, uint32_t *nregids,
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China HAL_CTRY_CODE cc, uint_t modeSelect,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Calibrate noise floor data following a channel scan or similar.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * This must be called prior retrieving noise floor data.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern void ath_hal_process_noisefloor(struct ath_hal *ah);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return bit mask of wireless modes supported by the hardware.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern uint32_t ath_hal_getwirelessmodes(struct ath_hal *, HAL_CTRY_CODE);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Calculate the transmit duration of a frame.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern uint16_t ath_hal_computetxtime(struct ath_hal *,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc const HAL_RATE_TABLE *rates, uint32_t frameLen,
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc uint16_t rateix, HAL_BOOL shortPreamble);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/*
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Return if device is public safety.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern HAL_BOOL ath_hal_ispublicsafetysku(struct ath_hal *);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China/*
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China * Return if device is operating in 900 MHz band.
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China */
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing Chinaextern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *);
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Convert between IEEE channel number and channel frequency
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * using the specified channel flags; e.g. CHANNEL_2GHZ.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxcextern int ath_hal_mhz2ieee(struct ath_hal *, uint32_t mhz, uint32_t flags);
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return a version string for the HAL release.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern char ath_hal_version[];
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Return a NULL-terminated array of build/configuration options.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xcextern const char *ath_hal_buildopts[];
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc/*
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc * Macros to encapsulated HAL functions.
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc */
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_RESET(_ah, _opmode, _chan, _outdoor, _pstatus) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_PHYDISABLE(_ah) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_phyDisable)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETCAPABILITY(_ah, _cap, _param, _result) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_SETCAPABILITY(_ah, _type, _cap, _param, _status) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China ((*(_ah)->ah_setCapability)((_ah), (_type), (_cap), (_param), \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China (_status)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETREGDOMAIN(_ah, _prd) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_REG_DMN, 0, (_prd))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETCOUNTRYCODE(_ah, _pcc) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (*(_pcc) = (_ah)->ah_countryCode)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETRATETABLE(_ah, _mode) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETMAC(_ah, _mac) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETMAC(_ah, _mac) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_INTRSET(_ah, _mask) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_INTRGET(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getInterrupts)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_INTRPEND(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_isInterruptPending)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETISR(_ah, _pmask) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_UPDATETXTRIGLEVEL(_ah, _inc) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_SETPOWER(_ah, _mode) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_KEYRESET(_ah, _ix) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_KEYSET(_ah, _ix, _pk, _mac) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_KEYISVALID(_ah, _ix) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_KEYSETMAC(_ah, _ix, _mac) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_KEYCACHESIZE(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getKeyCacheSize)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETRXFILTER(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getRxFilter)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETRXFILTER(_ah, _filter) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETMCASTFILTER(_ah, _mfilt0, _mfilt1) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_WAITFORBEACON(_ah, _bf) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_PUTRXBUF(_ah, _bufaddr) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETTSF32(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getTsf32)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETTSF64(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getTsf64)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_RESETTSF(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_resetTsf)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_RXENA(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_enableReceive)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_PUTTXBUF(_ah, _q, _bufaddr) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETTXBUF(_ah, _q) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getTxDP)((_ah), (_q)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETRXBUF(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getRxDP)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_TXSTART(_ah, _q) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_startTxDma)((_ah), (_q)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETCHANNEL(_ah, _chan) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setChannel)((_ah), (_chan)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_CALIBRATE(_ah, _chan, _iqcal) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETLEDSTATE(_ah, _state) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setLedState)((_ah), (_state)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_BEACONINIT(_ah, _nextb, _bperiod) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_BEACONRESET(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_BEACONTIMERS(_ah, _beacon_state) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_beacon_state)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETASSOCID(_ah, _bss, _associd) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETOPMODE(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setPCUConfig)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_STOPTXDMA(_ah, _qnum) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_STOPPCURECV(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_stopPcuReceive)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_STARTPCURECV(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_startPcuReceive)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_STOPDMARECV(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_stopDmaReceive)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_DUMPSTATE(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_dumpState)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_DUMPEEPROM(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_dumpEeprom)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_DUMPRFGAIN(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_dumpRfGain)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_DUMPANI(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_dumpAni)((_ah)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETUPTXQUEUE(_ah, _type, _irq) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_RESETTXQUEUE(_ah, _q) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_RELEASETXQUEUE(_ah, _q) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_GETTXQUEUEPROPS(_ah, _q, _qi) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_SETTXQUEUEPROPS(_ah, _q, _qi) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_HASVEOL(_ah) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_GETRFGAIN(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_getRfGain)((_ah)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_RXMONITOR(_ah, _arg, _chan) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_SETSLOTTIME(_ah, _us) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETUPBEACONDESC(_ah, _ds, _opmode, _flen, _hlen, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc _rate, _antmode) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (_flen), (_hlen), (_rate), (_antmode)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETUPRXDESC(_ah, _ds, _size, _intreq) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_RXPROCDESC(_ah, _ds, _dspa, _dsnext, _rs) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETUPTXDESC(_ah, _ds, _plen, _hlen, _atype, _txpow, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc _txr0, _txtr0, _keyix, _ant, _flags, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc _rtsrate, _rtsdura) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_SETUPXTXDESC(_ah, _ds, \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_FILLTXDESC(_ah, _ds, _l, _first, _last, _ath_desc) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (_ath_desc)))
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_TXPROCDESC(_ah, _ds, _ts) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#define ATH_HAL_CIPHERSUPPORTED(_ah, _cipher) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_HASTKIPSPLIT(_ah) \
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_GETTKIPSPLIT(_ah) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China#define ATH_HAL_SETTKIPSPLIT(_ah, _v) \
129d67acdc2d029d3d6cff4022c0c26c81c76f89lin wang - Sun Microsystems - Beijing China (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_HASRFSILENT(ah) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_GETRFKILL(_ah) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_SETRFKILL(_ah, _onoff) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_GETRFSILENT(_ah, _prfsilent) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_SETRFSILENT(_ah, _rfsilent) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#if HAL_ABI_VERSION < 0x05120700
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_PROCESS_NOISEFLOOR(_ah)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_GETCHANNOISE(_ah, _c) (-96)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_CAP_TPC_ACK 100
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_CAP_TPC_CTS 101
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#else
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define ATH_HAL_GETCHANNOISE(_ah, _c) \
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#endif
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#if HAL_ABI_VERSION < 0x05122200
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc#endif
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#ifdef __cplusplus
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc}
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc
7a1306a70fee0e017a445bde1dcfd1997f691cf4xc#endif /* _ATH_HAL_H */