5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * CDDL HEADER START
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * The contents of this file are subject to the terms of the
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Common Development and Distribution License (the "License").
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * You may not use this file except in compliance with the License.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * See the License for the specific language governing permissions
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * and limitations under the License.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * When distributing Covered Code, include this CDDL HEADER in each
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * If applicable, add the following below this CDDL HEADER, with the
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * fields enclosed by brackets "[]" replaced with your own identifying
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * information: Portions Copyright [yyyy] [name of copyright owner]
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * CDDL HEADER END
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Copyright (c) 2012 Gary Mills
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Use is subject to license terms.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * All rights reserved.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Redistribution and use in source and binary forms, with or without
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * modification, are permitted provided that the following conditions
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * 1. Redistributions of source code must retain the above copyright
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * notice unmodified, this list of conditions, and the following
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * disclaimer.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * 2. Redistributions in binary form must reproduce the above copyright
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * notice, this list of conditions and the following disclaimer in the
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * documentation and/or other materials provided with the distribution.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * SUCH DAMAGE.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Millsstatic ddi_dma_attr_t atge_l1c_dma_attr_tx_desc = {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0, /* dma_attr_addr_lo */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0 /* dma_attr_flags */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Millsstatic ddi_dma_attr_t atge_l1c_dma_attr_rx_desc = {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0, /* dma_attr_addr_lo */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0 /* dma_attr_flags */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0, /* dma_attr_addr_lo */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0 /* dma_attr_flags */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0, /* dma_attr_addr_lo */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0 /* dma_attr_flags */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0, /* dma_attr_addr_lo */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills 0 /* dma_attr_flags */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills l1c = kmem_zalloc(sizeof (atge_l1c_data_t), KM_SLEEP);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Allocate TX ring descriptor.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills sizeof (struct ether_header) + VLAN_TAGSZ + ETHERFCSL;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_tx_ring = kmem_alloc(sizeof (atge_ring_t), KM_SLEEP);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_tx_desc,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "DMA allocation failed for TX"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " desc ring");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Allocate DMA buffers for TX ring.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills err = atge_alloc_buffers(atgep->atge_tx_ring, ATGE_TX_RING_CNT,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "DMA allocation failed for"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " TX Ring");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Allocate RX ring.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills sizeof (struct ether_header) + VLAN_TAGSZ + ETHERFCSL;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills l1c->atge_rx_ring = kmem_alloc(sizeof (atge_ring_t), KM_SLEEP);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_rx_desc,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "DMA allocation failed"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " for RX Ring");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Allocate DMA buffers for RX ring.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills err = atge_alloc_buffers(l1c->atge_rx_ring, L1C_RX_RING_CNT,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "DMA allocation failed for"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " RX buffers");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Allocate CMB used for fetching interrupt status data.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_DB(("%s: %s() L1C_CMB_BLOCK_SZ : 0x%x", atgep->atge_name,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_cmb,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "DMA allocation failed for CMB");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * RR ring (Return Ring for RX and TX).
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_DB(("%s: %s() L1C_RR_RING_SZ : 0x%x", atgep->atge_name,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_rr,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "DMA allocation failed"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " for RX RR ring");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * SMB for statistics.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_DB(("%s: %s() L1C_SMB_BLOCK_SZ : 0x%x", atgep->atge_name,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills dma = atge_alloc_a_dma_blk(atgep, &atge_l1c_dma_attr_smb,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "DMA allocation failed for SMB");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_hw_stats = kmem_zalloc(sizeof (atge_l1c_smb_t), KM_SLEEP);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Free TX ring.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_free_buffers(atgep->atge_tx_ring, ATGE_TX_RING_CNT);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_free_a_dma_blk(atgep->atge_tx_ring->r_desc_ring);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills kmem_free(atgep->atge_tx_ring, sizeof (atge_ring_t));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Free RX ring.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_free_buffers(l1c->atge_rx_ring, L1C_RX_RING_CNT);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_free_a_dma_blk(l1c->atge_rx_ring->r_desc_ring);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills kmem_free(l1c->atge_rx_ring, sizeof (atge_ring_t));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Free the memory allocated for gathering hw stats.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills kmem_free(atgep->atge_hw_stats, sizeof (atge_l1c_smb_t));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Free the private area.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills l1c->atge_rx_ring->r_consumer = L1C_RX_RING_CNT - 1;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills for (i = 0; i < L1C_RX_RING_CNT; i++) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills (i * sizeof (l1c_rx_desc_t)));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills l1c->atge_rx_ring->r_buf_tbl[i]->cookie.dmac_laddress);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* No length field. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Let controller know availability of new Rx buffers. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills OUTL(atgep, ATGE_MBOX_RD0_PROD_IDX, l1c->atge_rx_ring->r_consumer);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_tx_ring->r_avail_desc = ATGE_TX_RING_CNT;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills bzero(atgep->atge_tx_ring->r_desc_ring->addr, ATGE_TX_RING_SZ);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills DMA_SYNC(atgep->atge_tx_ring->r_desc_ring, 0, 0, DDI_DMA_SYNC_FORDEV);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Clear WOL status and disable all WOL feature as WOL
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * would interfere Rx operation under normal environments.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_HI(r->r_desc_ring->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_LO(r->r_desc_ring->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* We don't use high priority ring. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_HI(r->r_desc_ring->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_LO(r->r_desc_ring->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* We use one Rx ring. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* RR Ring */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Let hardware split jumbo frames into alc_max_buf_sized chunks.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * if it do not fit the buffer size. Rx return descriptor holds
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * a counter that indicates how many fragments were made by the
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * hardware. The buffer size should be multiple of 8 bytes.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Since hardware has limit on the size of buffer size, always
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * use the maximum value.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * For strict-alignment architectures make sure to reduce buffer
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * size by 8 bytes to make room for alignment fixup.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills OUTL(atgep, L1C_RX_BUF_SIZE, RX_BUF_SIZE_MAX); /* XXX */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Set Rx return descriptor base addresses. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_LO(l1c->atge_l1c_rr->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* We use one Rx return ring. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_LO(l1c->atge_l1c_cmb->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_HI(l1c->atge_l1c_smb->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_ADDR_LO(l1c->atge_l1c_smb->cookie.dmac_laddress));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Set RX return ring (RR) counter.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Set Rx descriptor counter. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills (L1C_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Set Rx return descriptor counter. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills (L1C_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Set TX descriptor counter.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills (ATGE_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Reconfigure SRAM - Vendor magic. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Inform hardware that we have loaded DMA registers.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Configure interrupt moderation timer. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills reg = ATGE_USECS(atgep->atge_int_rx_mod) << IM_TIMER_RX_SHIFT;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills reg |= ATGE_USECS(atgep->atge_int_tx_mod) << IM_TIMER_TX_SHIFT;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * We don't want to automatic interrupt clear as task queue
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * for the interrupt should know interrupt status.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Clear RX stats first.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills i += sizeof (uint32_t);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Clear TX stats.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills i += sizeof (uint32_t);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Rx stats. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills stat->rx_control_frames += smb->rx_control_frames;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills stat->rx_pkts_truncated += smb->rx_pkts_truncated;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Tx stats. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills stat->tx_control_frames += smb->tx_control_frames;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills stat->tx_pkts_truncated += smb->tx_pkts_truncated;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Update global counters in atge_t.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_first_collisions += smb->tx_single_colls;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_multi_collisions += smb->tx_multi_colls * 2;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_tx_late_collisions += smb->tx_late_colls;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_ex_collisions += smb->tx_excess_colls;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_underflow += (smb->tx_underrun + smb->tx_desc_underrun);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * tx_pkts_truncated counter looks suspicious. It constantly
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * increments with no sign of Tx errors. Hence we don't factor it.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_macxmt_errors += smb->tx_late_colls + smb->tx_underrun;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_macrcv_errors += smb->rx_crcerrs + smb->rx_lenerrs +
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_DB(("%s: %s() called", atgep->atge_name, __func__));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Stop TX DMA engine. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills if (t == 0) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* This should be an FMA event. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, "stopping TX DMA Engine timeout");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_DB(("%s: %s() called", atgep->atge_name, __func__));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Stop RX DMA engine. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills if (t == 0) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* This should be an FMA event. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atge_error(atgep->atge_dip, " stopping RX DMA Engine timeout");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Receives (consumes) packets.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills mblk_t *mp = NULL, *rx_head = NULL, *rx_tail = NULL;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills uint32_t rdinfo, status, totlen, pktlen, slotlen;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills DMA_SYNC(l1c->atge_l1c_rr, 0, 0, DDI_DMA_SYNC_FORKERNEL);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills rx_rr = (l1c_rx_rdesc_t *)(l1c->atge_l1c_rr->addr +
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills (l1c->atge_l1c_rr_consumers * sizeof (l1c_rx_rdesc_t)));
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills rdinfo = ATGE_GET32(l1c->atge_l1c_rr, &rx_rr->rdinfo);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills status = ATGE_GET32(l1c->atge_l1c_rr, &rx_rr->status);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills "status : 0x%x, totlen : %d,"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " rx_cons : %d, nsegs : %d", atgep->atge_name, __func__,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills if ((status & (L1C_RRD_ERR_CRC | L1C_RRD_ERR_ALIGN |
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills l1c->atge_rx_ring->r_consumer %= L1C_RX_RING_CNT;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ASSERT(rx_cons >= 0 && rx_cons <= L1C_RX_RING_CNT);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * If there are more than one segments, then the first
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * segment should be of size MTU. We couldn't verify
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * this as our driver does not support changing MTU
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * or Jumbo Frames.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills slotlen = min(atgep->atge_max_frame_size, totlen);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_DB(("%s: %s() len : %d, rxcons : %d, pktlen : %d",
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills l1c->atge_rx_ring->r_consumer %= L1C_RX_RING_CNT;
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Tell the chip that this RR can be reused.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_INC_SLOT(l1c->atge_l1c_rr_consumers, L1C_RR_RING_CNT);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills DMA_SYNC(l1c->atge_l1c_rr, 0, 0, DDI_DMA_SYNC_FORDEV);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Let controller know availability of new Rx buffers.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills ATGE_DB(("%s: %s() PKT Recved -> r_consumer : %d, rx_cons : %d"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " atge_l1c_rr_consumers : %d",
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_name, __func__, l1c->atge_rx_ring->r_consumer,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * The interrupt handler for L1C chip.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills if (atgep->atge_chip_state & ATGE_CHIP_SUSPENDED) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills if (status == 0 || (status & atgep->atge_intrs) == 0) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Disable interrupts.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* clear PHY interrupt source before we ack interrupts */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills OUTL(atgep, ATGE_INTR_STATUS, status | L1C_INTR_DIS_INT);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Check if chip is running, only then do the work.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills if (atgep->atge_chip_state & ATGE_CHIP_RUNNING) {
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills "atge_l1c_rx_prod_cons : %d, atge_l1c_tx_prod_cons : %d"
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills " atge_l1c_rr_consumers : %d",
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills atgep->atge_name, __func__, l1c->atge_l1c_intr_status,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills l1c->atge_l1c_rx_prod_cons, l1c->atge_l1c_tx_prod_cons,
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Check for errors.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* This should be an FMA event. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills "L1C chip detected a fatal error, "
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills "DMA read error");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills "DMA write error");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills "Transmit queue error");
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* This should be an FMA event. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Device has failed fatally.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * It will not be restarted by the driver.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Re-enable interrupts. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* link down */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Pass the list of packets received from chip to MAC layer.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Let MAC start sending pkts if the downstream was asked to pause.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Sync descriptors. */
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills DMA_SYNC(atgep->atge_tx_ring->r_desc_ring, 0, 0, DDI_DMA_SYNC_FORDEV);
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills /* Kick. Assume we're using normal Tx priority queue. */