0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * CDDL HEADER START
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * The contents of this file are subject to the terms of the
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Common Development and Distribution License (the "License").
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * You may not use this file except in compliance with the License.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * See the License for the specific language governing permissions
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * and limitations under the License.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * When distributing Covered Code, include this CDDL HEADER in each
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * If applicable, add the following below this CDDL HEADER, with the
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * fields enclosed by brackets "[]" replaced with your own identifying
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * information: Portions Copyright [yyyy] [name of copyright owner]
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * CDDL HEADER END
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Use is subject to license terms.
5e8715b93d1d651ab2805b5e6e98b17df49fa92fGary Mills * Copyright (c) 2012 Gary Mills
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Statistics counters collected by the MAC
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra /* Rx stats. */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra /* Tx stats. */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra#define L1_RR_RING_CNT (ATGE_TX_RING_CNT + L1_RX_RING_CNT)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (sizeof (struct l1_rx_rdesc) * L1_RR_RING_CNT)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * All descriptors and CMB/SMB share the same high address.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * PHY registers.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * DMA CFG registers (L1 specific)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra#define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra#define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra#define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra/* CMB DMA Write Threshold Register */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra/* SMB auto DMA timer register */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra#define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra#define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra/* RX/TX count-down timer to trigger CMB-write. */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Useful macros.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (((x) & L1_RRD_NSEGS_MASK) >> L1_RRD_NSEGS_SHIFT)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (((x) & L1_RRD_CONS_MASK) >> L1_RRD_CONS_SHIFT)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (((x) & L1_RRD_CSUM_MASK) >> L1_RRD_CSUM_SHIFT)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra#endif /* _ATGE_L1_REG_H */