0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * CDDL HEADER START
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * The contents of this file are subject to the terms of the
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Common Development and Distribution License (the "License").
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * You may not use this file except in compliance with the License.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * See the License for the specific language governing permissions
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * and limitations under the License.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * When distributing Covered Code, include this CDDL HEADER in each
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * If applicable, add the following below this CDDL HEADER, with the
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * fields enclosed by brackets "[]" replaced with your own identifying
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * information: Portions Copyright [yyyy] [name of copyright owner]
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * CDDL HEADER END
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Use is subject to license terms.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misrastatic ddi_dma_attr_t atge_l1_dma_attr_tx_desc = {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0, /* dma_attr_addr_lo */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0 /* dma_attr_flags */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misrastatic ddi_dma_attr_t atge_l1_dma_attr_rx_desc = {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0, /* dma_attr_addr_lo */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0 /* dma_attr_flags */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0, /* dma_attr_addr_lo */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0 /* dma_attr_flags */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0, /* dma_attr_addr_lo */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0 /* dma_attr_flags */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0, /* dma_attr_addr_lo */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra 0 /* dma_attr_flags */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra l1 = kmem_zalloc(sizeof (atge_l1_data_t), KM_SLEEP);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Allocate TX ring descriptor.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra sizeof (struct ether_header) + VLAN_TAGSZ + ETHERFCSL;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_tx_ring = kmem_alloc(sizeof (atge_ring_t), KM_SLEEP);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra dma = atge_alloc_a_dma_blk(atgep, &atge_l1_dma_attr_tx_desc,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "DMA allocation failed for TX"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " desc ring");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Allocate DMA buffers for TX ring.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra err = atge_alloc_buffers(atgep->atge_tx_ring, ATGE_TX_RING_CNT,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "DMA allocation failed for"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Allocate RX ring.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra sizeof (struct ether_header) + VLAN_TAGSZ + ETHERFCSL;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra l1->atge_rx_ring = kmem_alloc(sizeof (atge_ring_t), KM_SLEEP);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra dma = atge_alloc_a_dma_blk(atgep, &atge_l1_dma_attr_rx_desc,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "DMA allocation failed"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " for RX Ring");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Allocate DMA buffers for RX ring.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra err = atge_alloc_buffers(l1->atge_rx_ring, L1_RX_RING_CNT,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "DMA allocation failed for"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " RX buffers");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Allocate CMB used for fetching interrupt status data.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() L1_CMB_BLOCK_SZ : %x", atgep->atge_name,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra dma = atge_alloc_a_dma_blk(atgep, &atge_l1_dma_attr_cmb,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "DMA allocation failed for CMB");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * RR ring (Return Ring for RX and TX).
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() L1_RR_RING_SZ : %x", atgep->atge_name,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra dma = atge_alloc_a_dma_blk(atgep, &atge_l1_dma_attr_rr,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "DMA allocation failed"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " for RX RR ring");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * SMB for statistics.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() L1_SMB_BLOCK_SZ : %x", atgep->atge_name,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra dma = atge_alloc_a_dma_blk(atgep, &atge_l1_dma_attr_smb,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "DMA allocation failed for SMB");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_hw_stats = kmem_zalloc(sizeof (atge_l1_smb_t), KM_SLEEP);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Free TX ring.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_free_buffers(atgep->atge_tx_ring, ATGE_TX_RING_CNT);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (atgep->atge_tx_ring->r_desc_ring != NULL) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_free_a_dma_blk(atgep->atge_tx_ring->r_desc_ring);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra kmem_free(atgep->atge_tx_ring, sizeof (atge_ring_t));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Free RX ring.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_free_buffers(l1->atge_rx_ring, L1_RX_RING_CNT);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_free_a_dma_blk(l1->atge_rx_ring->r_desc_ring);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra kmem_free(l1->atge_rx_ring, sizeof (atge_ring_t));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Free the memory allocated for gathering hw stats.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra kmem_free(atgep->atge_hw_stats, sizeof (atge_l1_smb_t));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra l1->atge_rx_ring->r_consumer = L1_RX_RING_CNT - 1;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra for (i = 0; i < L1_RX_RING_CNT; i++) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra rx = (l1_rx_desc_t *)(dma->addr + (i * sizeof (l1_rx_desc_t)));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra l1->atge_rx_ring->r_buf_tbl[i]->cookie.dmac_laddress);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (l1->atge_rx_ring->r_buf_tbl[i]->len & L1_RD_LEN_MASK) <<
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(dma, 0, L1_RX_RING_SZ, DDI_DMA_SYNC_FORDEV);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_tx_ring->r_avail_desc = ATGE_TX_RING_CNT;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra bzero(atgep->atge_tx_ring->r_desc_ring->addr, ATGE_TX_RING_SZ);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(atgep->atge_tx_ring->r_desc_ring, 0, ATGE_TX_RING_SZ,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(dma, 0, L1_RR_RING_SZ, DDI_DMA_SYNC_FORDEV);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(dma, 0, L1_SMB_BLOCK_SZ, DDI_DMA_SYNC_FORDEV);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(dma, 0, L1_CMB_BLOCK_SZ, DDI_DMA_SYNC_FORDEV);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ((l1->atge_rx_ring->r_consumer << MBOX_RD_PROD_IDX_SHIFT) &
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) |
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ((atgep->atge_tx_ring->r_producer << MBOX_TD_PROD_IDX_SHIFT) &
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_ADDR_HI(r->r_desc_ring->cookie.dmac_laddress));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_ADDR_LO(r->r_desc_ring->cookie.dmac_laddress));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_ADDR_LO(r->r_desc_ring->cookie.dmac_laddress));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra /* RR Ring */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_ADDR_LO(l1->atge_l1_rr->cookie.dmac_laddress));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_ADDR_LO(l1->atge_l1_cmb->cookie.dmac_laddress));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_ADDR_LO(l1->atge_l1_smb->cookie.dmac_laddress));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Set RX return ring (RR) counter.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ((L1_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Set TX descriptor counter.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (ATGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Inform hardware that we have loaded DMA registers.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Initialize mailbox register (mbox).
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(dma, 0, L1_SMB_BLOCK_SZ, DDI_DMA_SYNC_FORKERNEL);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra /* Rx stats. */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_bcast_frames += smb->rx_bcast_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_mcast_frames += smb->rx_mcast_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pause_frames += smb->rx_pause_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_control_frames += smb->rx_control_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pkts_truncated += smb->rx_pkts_truncated;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->rx_pkts_filtered += smb->rx_pkts_filtered;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra /* Tx stats. */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_bcast_frames += smb->tx_bcast_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_mcast_frames += smb->tx_mcast_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_pause_frames += smb->tx_pause_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_excess_defer += smb->tx_excess_defer;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_control_frames += smb->tx_control_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_single_colls += smb->tx_single_colls;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_excess_colls += smb->tx_excess_colls;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_desc_underrun += smb->tx_desc_underrun;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra stat->tx_pkts_truncated += smb->tx_pkts_truncated;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Update global counters in atge_t.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_brdcstrcv += smb->rx_bcast_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_brdcstxmt += smb->tx_bcast_frames;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_align_errors += smb->rx_alignerrs;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_first_collisions += smb->tx_single_colls;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_multi_collisions += smb->tx_multi_colls * 2;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_tx_late_collisions += smb->tx_late_colls;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_ex_collisions += smb->tx_excess_colls;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_toolong_errors += smb->rx_lenerrs;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_underflow += (smb->tx_underrun + smb->tx_desc_underrun);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_collisions += smb->tx_single_colls +
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * tx_pkts_truncated counter looks suspicious. It constantly
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * increments with no sign of Tx errors. Hence we don't factor it.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_macxmt_errors += smb->tx_late_colls + smb->tx_underrun;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_macrcv_errors += smb->rx_crcerrs + smb->rx_lenerrs +
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(dma, 0, L1_SMB_BLOCK_SZ, DDI_DMA_SYNC_FORDEV);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() called", atgep->atge_name, __func__));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra /* Stop TX DMA engine. */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (t == 0) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, "stopping TX DMA Engine timeout");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() called", atgep->atge_name, __func__));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra /* Stop RX DMA engine. */
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra for (t = ATGE_RESET_TIMEOUT; t > 0; t--) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (t == 0) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_error(atgep->atge_dip, " stopping RX DMA Engine timeout");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Receives (consumes) packets.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra mblk_t *mp = NULL, *rx_head = NULL, *rx_tail = NULL;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra uint32_t index, flags, totlen, pktlen, slotlen;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(l1->atge_l1_rr, 0, L1_RR_RING_SZ, DDI_DMA_SYNC_FORKERNEL);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra while (l1->atge_l1_rr_consumers != l1->atge_l1_rx_prod_cons) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra rx_rr = (l1_rx_rdesc_t *)(l1->atge_l1_rr->addr +
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (l1->atge_l1_rr_consumers * sizeof (l1_rx_rdesc_t)));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra index = ATGE_GET32(l1->atge_l1_rr, &rx_rr->index);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra flags = ATGE_GET32(l1->atge_l1_rr, &rx_rr->flags);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra totlen = L1_RX_BYTES(ATGE_GET32(l1->atge_l1_rr, &rx_rr->len));
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() PKT -- index : %d, flags : %x, totlen : %d,"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " rx_cons : %d, nsegs : %d", atgep->atge_name, __func__,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (flags & (L1_RRD_CRC | L1_RRD_CODE | L1_RRD_DRIBBLE |
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra L1_RRD_RUNT | L1_RRD_OFLOW | L1_RRD_TRUNC)) != 0) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra l1->atge_rx_ring->r_consumer %= L1_RX_RING_CNT;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ASSERT(rx_cons >= 0 && rx_cons <= L1_RX_RING_CNT);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * If there are more than one segments, then the first
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * segment should be of size MTU. We couldn't verify
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * this as our driver does not support changing MTU
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * or Jumbo Frames.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() PKT mp == NULL totlen : %d",
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra for (cnt = 0, pktlen = 0; cnt < nsegs; cnt++) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() len : %d, rxcons : %d, pktlen : %d",
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra l1->atge_rx_ring->r_consumer %= L1_RX_RING_CNT;
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Tell the chip that this RR can be reused.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_INC_SLOT(l1->atge_l1_rr_consumers, L1_RR_RING_CNT);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(l1->atge_rx_ring->r_desc_ring, 0, L1_RX_RING_SZ,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra DMA_SYNC(l1->atge_l1_rr, 0, L1_RR_RING_SZ, DDI_DMA_SYNC_FORDEV);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() PKT Recved -> r_consumer : %d, rx_cons : %d"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " atge_l1_rr_consumers : %d",
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_name, __func__, l1->atge_rx_ring->r_consumer,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * The interrupt handler for L1 chip.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (atgep->atge_chip_state & ATGE_CHIP_SUSPENDED) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (status == 0 || (status & atgep->atge_intrs) == 0) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Disable interrupts.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra OUTL(atgep, ATGE_INTR_STATUS, status | INTR_DIS_INT);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Check if chip is running, only then do the work.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (atgep->atge_chip_state & ATGE_CHIP_RUNNING) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_GET32(l1->atge_l1_cmb, &cmb->intr_status);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (ATGE_GET32(l1->atge_l1_cmb, &cmb->rx_prod_cons) &
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (ATGE_GET32(l1->atge_l1_cmb, &cmb->tx_prod_cons) &
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra ATGE_DB(("%s: %s() atge_l1_intr_status : %x, "
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra "atge_l1_rx_prod_cons : %d, atge_l1_tx_prod_cons : %d"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " atge_l1_rr_consumers : %d",
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atgep->atge_name, __func__, l1->atge_l1_intr_status,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra l1->atge_l1_rx_prod_cons, l1->atge_l1_tx_prod_cons,
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Inform the hardware that CMB was served.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * We must check for RX Overflow condition and restart the
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * chip. This needs to be done only when producer and consumer
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * counters are same for the RR ring (Return RX).
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if ((l1->atge_l1_intr_status & (INTR_CMB_RX | INTR_MAC_RX)) &&
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra (l1->atge_l1_rr_consumers == l1->atge_l1_rx_prod_cons))) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " atge_l1_rx_prod_cons : %d,"
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra " l1->atge_l1_rr_consumers : %d",
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (l1->atge_l1_intr_status & (INTR_CMB_TX | INTR_MAC_TX)) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra atge_tx_reclaim(atgep, l1->atge_l1_tx_prod_cons);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra "DMA transfer error");
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra OUTL(atgep, ATGE_INTR_STATUS, INTR_DIS_DMA | INTR_DIS_SM);
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra if (status & INTR_GPHY || atgep->atge_flags & ATGE_MII_CHECK) {
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Pass the list of packets received from chip to MAC layer.
0eb090a7674ebcdcb1c35501097edeb5f2395459Saurabh Misra * Let MAC start sending pkts if the downstream was asked to pause.