arn_phy.c revision dd1de3740722a4b99a74005255effebbd20a6d70
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "arn_core.h"
#include "arn_hw.h"
#include "arn_reg.h"
#include "arn_phy.h"
/* ARGSUSED */
void
int regWrites)
{
/* LINTED: E_CONSTANT_CONDITION */
}
{
uint32_t channelSel = 0;
uint32_t bModeSynth = 0;
uint32_t aModeRefSel = 0;
struct chan_centers centers;
if (freq < 4800) {
bModeSynth = 0;
bModeSynth = 1;
} else {
arn_problem("%s: invalid channel %u MHz\n",
return (B_FALSE);
}
if (freq == 2484) {
} else {
}
} else if ((freq % 10) == 0) {
else
} else if ((freq % 5) == 0) {
} else {
return (B_FALSE);
}
reg32 =
(1 << 5) | 0x1;
return (B_TRUE);
}
struct ath9k_channel *chan)
{
struct chan_centers centers;
reg32 &= 0xc0000000;
if (freq < 4800) {
bMode = 1;
fracMode = 1;
aModeRefSel = 0;
if (freq == 2484) {
} else {
}
} else {
bMode = 0;
fracMode = 0;
if ((freq % 20) == 0) {
aModeRefSel = 3;
} else if ((freq % 10) == 0) {
aModeRefSel = 2;
} else {
aModeRefSel = 0;
fracMode = 1;
refDivA = 1;
}
if (!fracMode) {
}
}
(bMode << 29) |
return (B_TRUE);
}
static void
{
while (bitsLeft > 0) {
(column * 8);
bitPosition = 0;
arrayEntry++;
}
}
{
/* LINTED E_FUNC_SET_NOT_USED */
int regWrites = 0;
if (AR_SREV_9280_10_OR_LATER(ah))
return (B_TRUE);
{
int i;
ahp->ah_analogBank6Data[i] =
}
}
if (eepMinorRev >= 2) {
if (IS_CHAN_2GHZ(chan)) {
} else {
}
}
return (B_TRUE);
}
void
{
}
}
}
}
}
}
}
}
}
}
{
if (!AR_SREV_9280_10_OR_LATER(ah)) {
kmem_zalloc((sizeof (uint32_t) *
kmem_zalloc((sizeof (uint32_t) *
kmem_zalloc((sizeof (uint32_t) *
kmem_zalloc((sizeof (uint32_t) *
kmem_zalloc((sizeof (uint32_t) *
kmem_zalloc((sizeof (uint32_t) *
kmem_zalloc((sizeof (uint32_t) *
"cannot allocate RF banks\n"));
return (B_FALSE);
}
kmem_zalloc((sizeof (uint32_t) *
"cannot allocate ah_addac5416_21\n"));
return (B_FALSE);
}
ahp->ah_bank6Temp =
kmem_zalloc((sizeof (uint32_t) *
"cannot allocate ah_bank6Temp\n"));
return (B_FALSE);
}
}
return (B_TRUE);
}
/* ARGSUSED */
void
{
/* LINTED E_FUNC_SET_NOT_USED */
int i, regWrites = 0;
switch (ahp->ah_diversityControl) {
case ATH9K_ANT_FIXED_A:
break;
case ATH9K_ANT_FIXED_B:
break;
case ATH9K_ANT_VARIABLE:
default:
return;
}
#ifdef ALTER_SWITCH
#endif
}