arn_mac.c revision dd1de3740722a4b99a74005255effebbd20a6d70
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Atheros Communications Inc.
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "arn_core.h"
#include "arn_hw.h"
#include "arn_reg.h"
#include "arn_phy.h"
/* ARGSUSED */
static void
struct ath9k_tx_queue_info *qi)
{
"%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
}
void
{
int i;
for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
if (i % 4 == 0)
}
"Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"));
for (i = 0; i < ATH9K_NUM_QUEUES;
if (i == 8) {
qcuOffset = 0;
qcuBase++;
}
if (i == 6) {
dcuOffset = 0;
dcuBase++;
}
"%2d %2x %1x %2x %2x\n",
}
"qcu_stitch state: %2x qcu_fetch state: %2x\n",
"qcu_complete state: %2x dcu_complete state: %2x\n",
"dcu_arb state: %2x dcu_fp state: %2x\n",
"chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
"txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
"txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
}
{
}
{
return (B_TRUE);
}
{
"tramist queue is %u\n", q));
return (B_TRUE);
}
{
if (npend == 0) {
npend = 1;
}
return (npend);
}
{
return (B_FALSE);
if (bIncTrigLevel) {
if (curLevel < MAX_TX_FIFO_THRESHOLD)
newLevel++;
} else if (curLevel > MIN_TX_FIFO_THRESHOLD)
newLevel--;
}
{
if (ath9k_hw_numtxpending(ah, q) == 0)
break;
drv_usecwait(100);
}
if (ath9k_hw_numtxpending(ah, q)) {
"%s: Num of pending TX Frames %d on Q %d\n",
for (j = 0; j < 2; j++) {
break;
"%s: TSF have moved while trying to set "
"quiet time TSF: 0x%08x\n",
}
drv_usecwait(200);
wait = 1000;
while (ath9k_hw_numtxpending(ah, q)) {
if ((--wait) == 0) {
"%s: Failed to stop Tx DMA in 100 "
"msec after killing last frame\n",
__func__));
break;
}
drv_usecwait(100);
}
}
return (wait != 0);
}
/* ARGSUSED */
{
if (firstSeg) {
} else if (lastSeg) {
} else {
}
return (B_TRUE);
}
/* ARGSUSED */
void
{
}
int
{
return (EINPROGRESS);
}
}
}
}
"arn: ATH9K_TXERR_TIMER_EXPIRED\n"));
}
}
}
}
}
case 0:
break;
case 1:
break;
case 2:
break;
case 3:
break;
}
return (0);
}
void
{
if (txPower > 63)
txPower = 63;
if (AR_SREV_9285(ah)) {
}
}
/* ARGSUSED */
void
struct ath9k_11n_rate_series series[],
{
(void) nseries;
(void) rtsctsDuration;
if (flags & ATH9K_TXDESC_RTSENA) {
ds_ctl0 &= ~AR_CTSEnable;
ds_ctl0 |= AR_RTSEnable;
} else {
ds_ctl0 &= ~AR_RTSEnable;
ds_ctl0 |= AR_CTSEnable;
}
} else {
}
(durUpdateEn ? AR_DurUpdateEna : 0) |
SM(0, AR_BurstDur);
}
/* ARGSUSED */
void
{
}
/* ARGSUSED */
void
{
unsigned int ctl6;
ctl6 &= ~AR_PadDelim;
}
/* ARGSUSED */
void
{
}
/* ARGSUSED */
void
{
}
/* ARGSUSED */
void
{
}
/* ARGSUSED */
void
{
if (vmf)
else
}
void
{
}
const struct ath9k_tx_queue_info *qinfo)
{
struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) {
__func__, q));
return (B_FALSE);
}
__func__));
return (B_FALSE);
}
else
} else
} else
if (qinfo->tqi_shretry != 0)
else
if (qinfo->tqi_lgretry != 0)
else
switch (qinfo->tqi_subtype) {
case ATH9K_WME_UPSD:
break;
default:
break;
}
return (B_TRUE);
}
struct ath9k_tx_queue_info *qinfo)
{
struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) {
"invalid queue num %u\n", q));
return (B_FALSE);
}
"inactive queue\n"));
return (B_FALSE);
}
return (B_TRUE);
}
int
const struct ath9k_tx_queue_info *qinfo)
{
struct ath9k_tx_queue_info *qi;
int q;
switch (type) {
case ATH9K_TX_QUEUE_BEACON:
break;
case ATH9K_TX_QUEUE_CAB:
break;
case ATH9K_TX_QUEUE_PSPOLL:
q = 1;
break;
case ATH9K_TX_QUEUE_UAPSD:
break;
case ATH9K_TX_QUEUE_DATA:
for (q = 0; q < pCap->total_queues; q++)
break;
if (q == pCap->total_queues) {
"arn: ath9k_hw_setuptxqueue(): "
"no available tx queue\n"));
return (-1);
}
break;
default:
"arn: ath9k_hw_setuptxqueue(): "
"bad tx queue type %u\n", type));
return (-1);
}
"queue %u\n", q));
"tx queue %u already active\n", q));
return (-1);
}
qi->tqi_physCompBuf = 0;
} else {
}
return (q);
}
{
struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) {
"invalid queue num %u\n", q));
return (B_FALSE);
}
"inactive queue %u\n", q));
return (B_FALSE);
}
"release queue %u\n", q));
return (B_TRUE);
}
{
struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) {
__func__, q));
return (B_FALSE);
}
__func__, q));
return (B_TRUE);
}
"%s: reset queue %u\n", __func__, q));
else
/* Nothing to do */
}
} else
if (qi->tqi_cbrPeriod) {
}
}
if (qi->tqi_burstTime &&
}
}
}
case ATH9K_TX_QUEUE_BEACON:
break;
case ATH9K_TX_QUEUE_CAB:
break;
case ATH9K_TX_QUEUE_PSPOLL:
break;
case ATH9K_TX_QUEUE_UAPSD:
break;
default:
break;
}
}
else
else
else
else
else
return (B_TRUE);
}
/* ARGSUSED */
int
{
struct ar5416_desc ads;
return (EINPROGRESS);
else
}
return (0);
}
{
if (flags & ATH9K_RXDESC_INTREQ)
return (B_TRUE);
}
{
if (set) {
AR_OBS_BUS_1_RX_STATE, 0)) {
"%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
return (B_FALSE);
}
} else {
}
return (B_TRUE);
}
void
{
}
void
{
}
void
{
}
void
{
}
{
"dma failed to stop in 10ms\n"
"AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
return (B_FALSE);
} else {
return (B_TRUE);
}
}