hci1394_ixl_update.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 1999-2002 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Isochronous IXL update routines.
* Routines used to dynamically update a compiled and presumably running
* IXL program.
*/
#include <sys/tnf_probe.h>
/* local defines for hci1394_ixl_update_prepare return codes */
#define IXL_PREP_READY 1
#define IXL_PREP_SUCCESS 0
#define IXL_PREP_FAILURE (-1)
/*
* variable used to indicate the number of times update will wait for
* interrupt routine to complete.
*/
int hci1394_upd_retries_before_fail = 50;
/* IXL runtime update static functions */
/*
* IXL commands and included fields which can be updated
* IXL1394_OP_CALLBACK: callback(), callback_data
* IXL1394_OP_JUMP: label
* IXL1394_OP_RECV_PKT ixl_buf, size, mem_bufp
* IXL1394_OP_RECV_PKT_ST ixl_buf, size, mem_bufp
* IXL1394_OP_RECV_BUF(ppb) ixl_buf, size, pkt_size, mem_bufp, buf_offset
* IXL1394_OP_RECV_BUF(fill) ixl_buf, size, pkt_size, mem_bufp, buf_offset
* IXL1394_OP_SEND_PKT ixl_buf, size, mem_bufp
* IXL1394_OP_SEND_PKT_ST ixl_buf, size, mem_bufp
* IXL1394_OP_SEND_PKT_WHDR_ST ixl_buf, size, mem_bufp
* IXL1394_OP_SEND_BUF ixl_buf, size, pkt_size, mem_bufp, buf_offset
* IXL1394_OP_SET_TAGSYNC tag, sync
* IXL1394_OP_SET_SKIPMODE skipmode, label
*
* IXL commands which can not be updated
* IXL1394_OP_LABEL
* IXL1394_OP_SEND_HDR_ONLY
* IXL1394_OP_SEND_NOPKT
* IXL1394_OP_STORE_VALUE
* IXL1394_OP_STORE_TIMESTAMP
* IXL1394_OP_SET_SYNCWAIT
*/
/*
* hci1394_ixl_update
* main entrypoint into dynamic update code: initializes temporary
* update variables, evaluates request, coordinates with potentially
* simultaneous run of interrupt stack, evaluates likelyhood of success,
* performs the update, checks if completed, performs cleanup
* resulting from coordination with interrupt stack.
*/
int
{
int prepstatus;
int ret;
/* save caller specified values in update work variables structure */
/* initialize remainder of update work variables */
uv.hci_offset = 0;
uv.hdr_offset = 0;
/* set done ok return status */
uv.upd_status = 0;
/* evaluate request and prepare to perform update */
if (prepstatus != IXL_PREP_READY) {
/*
* if either done or nothing to do or an evaluation error,
* return update status
*/
/* if prep evaluation error, return failure */
if (prepstatus != IXL_PREP_SUCCESS) {
"IXL_PREP_FAILURE");
return (DDI_FAILURE);
}
/* if no action or update done, return update successful */
return (DDI_SUCCESS);
}
/* perform update processing reservation of interrupt context */
if (ret != DDI_SUCCESS) {
/* error acquiring control of context - return */
return (DDI_FAILURE);
}
/* perform update risk analysis */
/*
* return, if excessive risk or dma execution processing lost
* (note: caller risk override not yet implemented)
*/
/* attempt intr processing cleanup, unless err is dmalost */
(void) hci1394_ixl_update_endup(&uv);
} else {
/*
* error is dmalost, just release interrupt context.
* take the lock here to ensure an atomic read, modify,
* write of the "intr_flags" field while we try to
* clear the "in update" flag. protects from the
* interrupt routine.
*/
}
return (DDI_FAILURE);
}
/* perform requested update */
/*
* if non-completion condition, return update status
* attempt interrupt processing cleanup first
*/
(void) hci1394_ixl_update_endup(&uv);
return (DDI_FAILURE);
}
/* evaluate update completion, setting completion status */
/*
* update failed - bad, just release interrupt context
* take the lock here too (jsut like above) to ensure an
* atomic read, modify, write of the "intr_flags" field
* while we try to clear the "in update" flag. protects
* from the interrupt routine.
*/
/* if DMA stopped or lost, formally stop context */
}
return (DDI_FAILURE);
}
/* perform interrupt processing cleanup */
/* return update completion status */
"");
return (DDI_SUCCESS);
}
/*
* hci1394_ixl_update_enable
* Used to coordinate dynamic update activities with simultaneous
* interrupt handler processing, while holding the context mutex
* for as short a time as possible.
*/
static int
{
int status;
/* set arbitrary number of retries before giving up */
/*
* if waited for completion of interrupt processing generated callback,
* retry here
*/
remretries--;
/* failure if update processing is already in progress */
/*
* if have retried max number of times or if this update
* request is on the interrupt stack, which means that
* the callback function of the target driver initiated
* the update, set update failure.
*/
if ((remretries <= 0) ||
} else {
/*
* if not on interrupt stack and retries not
* exhausted, free mutex, wait a short time
* and then retry.
*/
drv_usecwait(1);
continue;
}
}
}
/* if context is available, reserve it for this update request */
if (status == DDI_SUCCESS) {
}
return (status);
}
/*
* hci1394_ixl_update_endup()
* The ending stage of coordinating with simultaneously running interrupts.
* Perform interrupt processing sync tasks if we (update) had blocked the
* interrupt out when it wanted a turn.
*/
static int
{
/*
* We don't need to grab the lock here because
* the "intr_flags" field is only modified in two
* ways - one in UPDATE and one in INTR routine. Since
* we know that it can't be modified simulataneously
* in another UDPATE thread - that is assured by the
* checks in "update_enable" - we would only be trying
* to protect against the INTR thread. And since we
* are going to clear a bit here (and check it again
* at the top of the loop) we are not really concerned
* about missing its being set by the INTR routine.
*/
if (status == HCI1394_IXL_INTR_DMALOST) {
/*
* Unlike above, we do care here as we are
* trying to clear the "in update" flag, and
* we don't want that lost because the INTR
* routine is trying to set its flag.
*/
continue;
}
}
}
}
/* if DMA stopped or lost, formally stop context */
if (status == HCI1394_IXL_INTR_DMASTOP) {
} else if (status == HCI1394_IXL_INTR_DMALOST) {
}
return (status);
}
/*
* hci1394_ixl_update_prepare()
* Preparation for the actual update (using temp uvp struct)
*/
static int
{
int ret;
/* both new and old ixl commands must be the same */
"EOPCODE_MISMATCH");
return (IXL_PREP_FAILURE);
}
/*
* perform evaluation and prepare update based on specific
* IXL command type
*/
switch (uvp->ixl_opcode) {
case IXL1394_OP_CALLBACK_U: {
/* perform update now without further evaluation */
/* nothing else to do, return with done ok status */
return (IXL_PREP_SUCCESS);
}
case IXL1394_OP_JUMP_U:
return (ret);
return (ret);
case IXL1394_OP_SET_TAGSYNC_U:
return (ret);
case IXL1394_OP_RECV_PKT_U:
case IXL1394_OP_RECV_PKT_ST_U:
return (ret);
case IXL1394_OP_RECV_BUF_U:
return (ret);
case IXL1394_OP_SEND_PKT_U:
case IXL1394_OP_SEND_PKT_ST_U:
return (ret);
case IXL1394_OP_SEND_BUF_U:
return (ret);
default:
/* ixl command being updated must be one of above, else error */
return (IXL_PREP_FAILURE);
}
}
/*
* hci1394_ixl_update_prep_jump()
* Preparation for update of an IXL1394_OP_JUMP_U command.
*/
static int
{
int err;
/* check if any change between new and old ixl jump command */
/* if none, return with done ok status */
return (IXL_PREP_SUCCESS);
}
/* new ixl jump command label must be ptr to valid ixl label or NULL */
/* if not jumping to label, return an error */
"EJUMP_NOT_TO_LABEL");
return (IXL_PREP_FAILURE);
}
/*
* follow exec path from new ixl jump command label to determine new
* jump destination ixl xfer command
*/
&ixlp);
/*
* get the bound address of the first descriptor block reached
* by the jump destination. (This descriptor is the first
* transfer command following the jumped-to label.) Set the
* descriptor's address (with Z bits) into jumpaddr.
*/
}
/*
* get associated xfer IXL command from compiler_privatep of old
* jump command
*/
/* if none, return an error */
"EORIG_IXL_CORRUPTED");
return (IXL_PREP_FAILURE);
}
/*
* get the associated IXL xfer command's last dma descriptor block
* last descriptor, then get hcihdr from its hdr field,
* removing interrupt enabled bits
*/
/* Sync the descriptor before we grab the header(s) */
if (err != DDI_SUCCESS) {
"EINTERNAL_ERROR: dma_sync() failed");
return (IXL_PREP_FAILURE);
}
/* set depth to last dma descriptor block & update count to 1 */
/*
* if there is only one dma descriptor block and IXL xfer command
* inited by a label or have found callbacks along the exec path to the
* new destination IXL xfer command, enable interrupt in hcihdr value
*/
}
}
/*
* if xfer type is xmit and skip mode for this for this xfer command is
* IXL1394_SKIP_TO_NEXT then set uvp->skipmode to IXL1394_SKIP_TO_NEXT
* and set uvp->skipxferp to uvp->jumpaddr and set uvp->hci_offset to
* offset from last dma descriptor to first dma descriptor
* (where skipaddr goes).
*
* update perform processing will have to set skip branch address to
* same location as jump destination in this case.
*/
/*
* calc hci_offset to first descriptor (where skipaddr
* goes) of dma descriptor block from current (last)
* descriptor of the descriptor block (accessed in
* xfer_ctl dma_descp of IXL xfer command)
*/
/*
* send header only is (Z bits - 2)
* descriptor components back from last one
*/
} else {
/*
* all others are (Z bits - 1) descriptor
* components back from last component
*/
}
}
}
return (IXL_PREP_READY);
}
/*
* hci1394_ixl_update_prep_set_skipmode()
* Preparation for update of an IXL1394_OP_SET_SKIPMODE_U command.
*/
static int
{
/* check if new set skipmode is change from old set skipmode */
if (new_set_skipmode_ixlp->skipmode ==
if ((new_set_skipmode_ixlp->skipmode !=
/* No change, return with done ok status */
return (IXL_PREP_SUCCESS);
}
}
/* find associated ixl xfer commnd by following old ixl links */
IXL1394_OPF_ISXFER) == 0) ||
}
/* return an error if no ixl xfer command found */
errmsg, "EORIG_IXL_CORRUPTED");
return (IXL_PREP_FAILURE);
}
/*
* get Z bits (number of descriptor components in descriptor block)
* from a dma bound addr in the xfer_ctl struct of the IXL xfer command
*/
if ((xferctlp = (hci1394_xfer_ctl_t *)
"EORIG_IXL_CORRUPTED");
return (IXL_PREP_FAILURE);
}
/*
* determine hci_offset to first component (where skipaddr goes) of
* dma descriptor block from current (last) descriptor component of
* desciptor block (accessed in xfer_ctl dma_descp of IXL xfer command)
*/
/*
* "send header only" is (Z bits - 2) descriptors back
* from last one
*/
} else {
/*
* all others are (Z bits - 1) descroptors back from
* last descriptor.
*/
}
/* set depth to zero and count to update all dma descriptors */
/* set new skipmode and validate */
/* return an error if invalid mode */
errmsg, "EBAD_SKIPMODE");
return (IXL_PREP_FAILURE);
}
/* if mode is skip to label */
/* verify label field is valid ixl label cmd */
IXL1394_OP_LABEL)) {
/* Error - not skipping to valid label */
return (IXL_PREP_FAILURE);
}
/*
* follow new skip exec path after label to next xfer
* IXL command
*/
(void) hci1394_ixl_find_next_exec_xfer(
/*
* set skip destination IXL xfer command.
* after update set into old set skip mode IXL compiler_privatep
*/
/*
* set skipaddr to be the first dma descriptor block's
* dma bound address w/Z bits
*/
xferctlp = (hci1394_xfer_ctl_t *)
}
}
/*
* if mode is skip to next, get skipaddr for last dma descriptor block
*/
/* follow normal exec path to next xfer ixl command */
/*
* get skip_next destination IXL xfer command
* (for last iteration)
*/
/*
* set skipaddr to first dma descriptor block's
* dma bound address w/Z bits
*/
xferctlp = (hci1394_xfer_ctl_t *)
}
}
return (IXL_PREP_READY);
}
/*
* hci1394_ixl_update_prep_set_tagsync()
* Preparation for update of an IXL1394_OP_SET_TAGSYNC_U command.
*/
static int
{
/* check if new set tagsync is change from old set tagsync. */
/* no change, return with done ok status */
return (IXL_PREP_SUCCESS);
}
/* find associated IXL xfer commnd by following old ixl links */
IXL1394_OPF_ISXFER) == 0) ||
}
/* return an error if no IXL xfer command found */
return (IXL_PREP_FAILURE);
}
/* is IXL xfer command an IXL1394_OP_SEND_NO_PKT? */
/* no update needed, return done ok status */
return (IXL_PREP_SUCCESS);
}
/*
* get Z bits (# of descriptor components in descriptor block) from
* any dma bound address in the xfer_ctl struct of the IXL xfer cmd
*/
if ((xferctlp = (hci1394_xfer_ctl_t *)
return (IXL_PREP_FAILURE);
}
/*
* determine hdr_offset from the current(last) descriptor of the
* DMA descriptor block to the descriptor where pkthdr1 goes
* by examining IXL xfer command
*/
/*
* if IXL send header only, the current (last)
* descriptor is the one
*/
uvp->hdr_offset = 0;
} else {
/*
* all others are the first descriptor (Z bits - 1)
* back from the last
*/
}
/* set depth to zero and count to update all dma descriptors */
return (IXL_PREP_READY);
}
/*
* hci1394_ixl_update_prep_recv_pkt()
* Preparation for update of an IXL1394_OP_RECV_PKT_U or
* IXL1394_OP_RECV_PKT_ST_U command.
*/
static int
{
int err;
/* check if any change between new and old IXL xfer commands */
/* no change. return with done ok status */
return (IXL_PREP_SUCCESS);
}
/* if new IXL buffer addrs are null, return error */
return (IXL_PREP_FAILURE);
}
/* if IXL xfer command is not xfer start command */
/*
* find IXL xfer start command in the compiler_privatep of the
* old IXL xfer command
*/
/* Error - no IXL xfer start command found */
return (IXL_PREP_FAILURE);
}
} else {
/* IXL xfer command is the IXL xfer start command */
}
/* check that xfer_ctl is present in the IXL xfer start command */
if ((xferctlp = (hci1394_xfer_ctl_t *)
/* Error - no xfer_ctl struct found */
return (IXL_PREP_FAILURE);
}
/* set depth to zero and count to 1 to update dma descriptor */
/*
* get Z bits (number of descriptors in descriptor block) from the DMA
* bound address in the xfer_ctl struct of the IXL xfer start cpmmand.
*/
/*
* set offset from the current(last) descriptor to the descriptor for
* this packet command
*/
/*
* set bufsize to the new IXL xfer size, and bufaddr to the new
* IXL xfer bufp
*/
/*
* new bufsize
*/
/* Sync the descriptor before we grab the header(s) */
if (err != DDI_SUCCESS) {
"EINTERNAL_ERROR: dma_sync() failed");
return (IXL_PREP_FAILURE);
}
return (IXL_PREP_READY);
}
/*
* hci1394_ixl_update_prep_recv_buf()
* Preparation for update of an IXL1394_OP_RECV_BUF_U command.
*/
static int
{
/* check if any change between new and old IXL xfer commands */
/* no change. return with done ok status */
return (IXL_PREP_SUCCESS);
}
}
/* if new IXL buffer addrs are null, return error */
return (IXL_PREP_FAILURE);
}
/*
* if not buffer fill mode, check that the new pkt_size > 0 and
* blocks required
*/
if ((new_xfer_buf_ixlp->pkt_size == 0) ||
/* count changes. return an error */
return (IXL_PREP_FAILURE);
}
}
/* set old IXL xfer command as the current IXL xfer command */
/* check that the xfer_ctl struct is present in IXL xfer command */
== NULL) {
/* return an error if no xfer_ctl struct is found for command */
return (IXL_PREP_FAILURE);
}
/* set depth to zero and count to update all dma descriptors */
/* set bufsize to new pkt_size (or to new size if buffer fill mode) */
} else {
}
/* set bufaddr to new ixl_buf */
/* set hcihdr reqcnt and hcistatus rescnt to new bufsize */
uvp->hci_offset = 0;
return (IXL_PREP_READY);
}
/*
* hci1394_ixl_update_prep_send_pkt()
* Preparation for update of an IXL1394_OP_SEND_PKT_U command,
* IXL1394_OP_SEND_PKT_ST_U command and IXL1394_OP_SEND_PKT_WHDR_ST_U
* command.
*/
static int
{
int err;
/* check if any change between new and old IXL xfer commands */
/* if none, return with done ok status */
return (IXL_PREP_SUCCESS);
}
/* if new ixl buffer addrs are null, return error */
return (IXL_PREP_FAILURE);
}
/* error if IXL1394_OP_SEND_PKT_WHDR_ST_U opcode and size < 4 */
return (IXL_PREP_FAILURE);
}
/* if IXL xfer command is not an IXL xfer start command */
/*
* find IXL xfer start command in the compiler_privatep of the
* old IXL xfer command
*/
/* error if no IXL xfer start command found */
return (IXL_PREP_FAILURE);
}
} else {
/* IXL xfer command is the IXL xfer start command */
}
/*
* get Z bits (number of descriptor components in the descriptor block)
* from a dma bound address in the xfer_ctl structure of the IXL
* xfer start command
*/
if ((xferctlp = (hci1394_xfer_ctl_t *)
return (IXL_PREP_FAILURE);
}
/* set depth to zero and count to 1 to update dma descriptor */
/*
* set offset to the header(first) descriptor from the
* current(last) descriptor
*/
/*
* set offset from the current(last) descriptor to the descriptor for
* this packet command
*/
/* set bufsize to new pkt buffr size, set bufaddr to new bufp */
/*
* if IXL1394_OP_SEND_PKT_WHDR_ST_U opcode, adjust size & buff,
* step over hdr
*/
}
/* Sync the descriptor before we grab the header(s) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORCPU);
if (err != DDI_SUCCESS) {
"EINTERNAL_ERROR: dma_sync() failed");
return (IXL_PREP_FAILURE);
}
return (IXL_PREP_FAILURE);
}
return (IXL_PREP_READY);
}
/*
* hci1394_ixl_update_prep_send_buf()
* Preparation for update of an IXL1394_OP_SEND_BUF_U command.
*/
static int
{
/* check if any change between new and old IXL xfer commands */
/* no change, return with done ok status */
return (IXL_PREP_SUCCESS);
}
/* if new IXL buffer addresses are null, return error */
return (IXL_PREP_FAILURE);
}
/*
* doesn't change the count of DMA descriptor blocks required
*/
if ((new_xfer_buf_ixlp->pkt_size == 0) ||
/* Error - new has different pkt count than old */
return (IXL_PREP_FAILURE);
}
/* set the old IXL xfer command as the current IXL xfer command */
/*
* get Z bits (number of descriptor components in descriptor block)
* from a DMA bound address in the xfer_ctl struct of the
* IXL xfer command
*/
if ((xferctlp = (hci1394_xfer_ctl_t *)
return (IXL_PREP_FAILURE);
}
/* set depth to zero and count to update all dma descriptors */
/*
* set offset to the header(first) descriptor from the current (last)
* descriptor.
*/
/* set offset to the only(last) xfer descriptor */
uvp->hci_offset = 0;
/* set bufsize to the new pkt_size, set bufaddr to the new bufp */
/*
* if IXL1394_OP_SEND_PKT_WHDR_ST_U opcode, adjust size & buff,
* step over header (a quadlet)
*/
}
/* set hcihdr to new bufsize */
/* set pkthdr2 to new bufsize */
return (IXL_PREP_READY);
}
/*
* hci1394_ixl_update_perform()
* performs the actual update into DMA memory.
*/
static int
{
int ii;
int err;
/*
* if no target ixl xfer command to be updated or it has
* no xfer_ctl struct, then internal error.
*/
((xferctlp = (hci1394_xfer_ctl_t *)
return (DDI_FAILURE);
}
/* perform update based on specific ixl command type */
switch (uvp->ixl_opcode) {
case IXL1394_OP_JUMP_U: {
/*
* set new hdr and new branch fields into last component of last
* dma descriptor block of ixl xfer cmd associated with
* ixl jump cmd
*/
hcidescp = (hci1394_desc_imm_t *)
dma_hdl =
/*
* if xfer type is send and skip mode is IXL1394__SKIP_TO_NEXT
* also set branch location into branch field of first
* component (skip to address) of last dma descriptor block
*/
}
/* Sync descriptor for device (desc was modified) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORDEV);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
/* set old ixl jump cmd label from new ixl jump cmd label */
break;
}
case IXL1394_OP_SET_SKIPMODE_U: {
/*
* if skip to next mode, save skip addr for last iteration
* thru dma descriptor blocks for associated ixl xfer command
*/
}
/*
* iterate through set of dma descriptor blocks for associated
* ixl xfer start cmd and set new skip address into first hci
* descriptor of each if skip next or skip self, first determine
* address in each iteration
*/
hcidescp = (hci1394_desc_imm_t *)
} else {
}
}
/* Sync descriptor for device (desc was modified) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORDEV);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
}
/*
* set old ixl set skip mode cmd mode and label from new ixl cmd
* set old ixl set skip mode cmd compilier_privatep to
* uvp->skipxferp
*/
break;
}
case IXL1394_OP_SET_TAGSYNC_U: {
/*
* iterate through set of descriptor blocks for associated IXL
* descriptor block)
*/
hcidescp = (hci1394_desc_imm_t *)
/* Sync descriptor for device (desc was modified) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORDEV);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
}
/*
* set old ixl set tagsync cmd tag & sync from new ixl set
* tagsync cmd
*/
break;
}
case IXL1394_OP_RECV_PKT_U:
case IXL1394_OP_RECV_PKT_ST_U: {
/*
* alter buffer address, count and rescount in ixl recv pkt cmd
* related hci component in dma descriptor block
*/
hcidescp = (hci1394_desc_imm_t *)
/* Sync the descriptor before we grab the status */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORCPU);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
/* change only low 1/2 word and leave status bits unchanged */
/* Sync descriptor for device (desc was modified) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORDEV);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
/*
* set old ixl recv pkt size and buffers from new
* ixl recv pkt command
*/
break;
}
case IXL1394_OP_RECV_BUF_U: {
/*
* iterate through set of descriptor blocks for this IXL xfer
* command altering buffer, count and rescount in each
*/
hcidescp = (hci1394_desc_imm_t *)
/*
* advance to next buffer segment, adjust over header
* if appropriate
*/
/* Sync the descriptor before we grab the header(s) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORCPU);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
/*
* this preserves interrupt enable bits, et al. in each
* descriptor block header.
*/
/*
* change only low 1/2 word leaving status bits
* unchanged
*/
/* Sync descriptor for device (desc was modified) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORDEV);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
}
/*
* set old ixl recv buf sizes and buffers from
* new ixl recv pkt cmd
*/
break;
}
case IXL1394_OP_SEND_PKT_U:
case IXL1394_OP_SEND_PKT_ST_U:
case IXL1394_OP_SEND_PKT_WHDR_ST_U: {
/*
* replace pkthdr2 in output more immediate (the first) hci
* descriptor in block, then alter buffer address and count in
*/
/* Sync descriptor for device (desc was modified) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORDEV);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
/*
* set old ixl recv pkt size and buffers from
* new ixl recv pkt cmd
*/
break;
}
case IXL1394_OP_SEND_BUF_U: {
/*
* iterate through set of descriptor blocks for this IXL xfer
* command replacing pkthdr2 in output more immediate
* (the first) hci descriptor block descriptor, then altering
* buffer address and count in each output last (the only other)
* hci descriptor block descriptor.
*/
hcidescp = (hci1394_desc_imm_t *)
/* advance to next buffer segment */
/* Sync the descriptor before we grab the header(s) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORCPU);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
/*
* this preserves interrupt enable bits, et al
* in each desc block hdr
*/
/* Sync descriptor for device (desc was modified) */
sizeof (hci1394_desc_imm_t), DDI_DMA_SYNC_FORDEV);
if (err != DDI_SUCCESS) {
return (DDI_FAILURE);
}
}
/*
* set old ixl recv buf sizes and buffers from
* new ixl recv pkt cmd
*/
break;
}
default:
/* ixl command being updated must be one of above, else error */
return (DDI_FAILURE);
}
/* hit the WAKE bit in the context control register */
0, 0, 0, 0, 0, 1 /* wake */);
} else {
0, 0, 0, 1 /* wake */);
}
/* perform update completed successfully */
return (DDI_SUCCESS);
}
/*
* hci1394_ixl_update_evaluate()
* Evaluate where the hardware is in running through the DMA descriptor
* blocks.
*/
static int
{
int ixldepth;
int ii;
ixldepth = 0xFFFFFFFF;
/*
* repeat until IXL execution status evaluation function returns error
* or until pointer to currently executing IXL command and its depth
* stablize
*/
/*
* call IXL execution status evaluation (ixl_dma_sync)
* function returning if error (HCI1394_IXL_INTR_DMALOST is
* only error condition).
*
* Note: interrupt processing function can only return one of
* the following statuses here:
* HCI1394_IXL_INTR_NOERROR, HCI1394_IXL_INTR_DMASTOP,
* HCI1394_IXL_INTR_DMALOST
*
* it can not return the following status here:
* HCI1394_IXL_INTR_NOADV
*
* Don't need to grab the lock here... for the same reason
* explained in hci1394_ixl_update_endup() above.
*/
/* return post-perform update failed status */
return (DDI_FAILURE);
}
}
/*
* if the currently executing IXL command is one of the IXL_MAX_LOCN
* locations saved before update was performed, return update
* successful status.
*/
return (DDI_SUCCESS);
}
}
/*
* else return post-perform update failed status.
* note: later can make more sophisticated evaluations about where
* execution processing went, and if update has really failed.
*/
return (DDI_FAILURE);
}
/*
* hci1394_ixl_update_analysis()
* Determine if the hardware is within the range we expected it to be.
* If so the update succeeded.
*/
static int
{
int ixldepth;
int ii;
int status;
ixldepth = 0xFFFFFFFF;
/*
* repeat until ixl execution status evaluation function returns error
* or until pointer to currently executing ixl command and its depth
* stablize.
*/
/*
* call ixl execution status evaluation (interrupt processing).
* set IXL1394_EIDU_PRE_UPD_DMALOST if status INTR_DMALOST and
* return.
*
* Note: interrupt processing function can only return one of
* the following statuses here:
* HCI1394_IXL_INTR_NOERROR, HCI1394_IXL_INTR_DMASTOP or
* HCI1394_IXL_INTR_DMALOST
*
* it can not return the following status here:
* HCI1394_IXL_INTR_NOADV
*
* Don't need to grab the lock here... for the same reason
* explained in hci1394_ixl_update_endup() above.
*/
if (status == HCI1394_IXL_INTR_DMALOST) {
/*
* set pre-update dma processing lost status and
* return error
*/
return (DDI_FAILURE);
}
}
/*
* save locations of currently executing ixl command and the
* 3 following it.
*/
/*
* if xfer_ixl_cmd associated with the IXL_command being updated is one
* of the saved (currently executing) IXL commands, risk is too great to
* perform update now, set IXL1394_ERISK_PROHIBITS_UPD status and
* return error.
*
* Note: later can implement more sophisticated risk override
* evaluations and processing.
*/
return (DDI_FAILURE);
}
}
/* is save for update to be performed, return ok status */
return (DDI_SUCCESS);
}
/*
* hci1394_ixl_update_set_locn_info()
* set up the local list of the IXL_MAX_LOCN next commandPtr locations we
* expect the hardware to get to in the next 125 microseconds.
*/
static void
{
int ixldepth;
int ii;
/*
* find next xfer start ixl command, starting with current ixl command
* where execution last left off
*/
/*
* if the current IXL command wasn't a xfer start command, then reset
* the depth to 0 for xfer command found
*/
ixldepth = 0;
/*
* save xfer start IXL command & its depth and also save location and
* depth of the next IXL_MAX_LOCN-1 xfer start IXL commands following
* it (if any)
*/
if (ixlp) {
/*
* if more dma commands generated by this xfer command
* still follow, use them. else, find the next xfer
* start IXL command and set its depth to 0.
*/
if (++ixldepth >= ((hci1394_xfer_ctl_t *)
(void) hci1394_ixl_find_next_exec_xfer(
ixldepth = 0;
}
}
}
}