ptops.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <amd64/amd64_page.h>
static amd64_mmumode_t mmus[] = {
{ 22, 10, 2, 1024 }, /* legacy 32-bit mode */
{ 39, 9, 4, 512 } /* long 64-bit mode */
};
{
}
{
return (IS_LARGEMAP(entry) ?
}
{
(entry & ~0xfffULL));
}
{
return (amd64_mmu_mode == AMD64_MODE_LONG64) ?
}
static uint64_t
{
mask);
if (!(ENTRY_VALID(entry))) {
/*
* If a page level is empty, set addr_inc to the shift
* value because in a sequential search we know the next
* (1 << level_shift) bytes are unmapped.
*/
while (shift >= 32)
if (addr_inc)
return (0);
}
/* Set addr_inc to pagesize found and return entry. */
while (shift >= 32)
if (addr_inc)
return (entry);
}
}
if (addr_inc)
return (0);
}
{
}
{
addr_inc));
}
{
}
{
}
void
{
amd64_panic("amd64_map_mem: map attempted into 64-bit VA "
"hole (va 0x%llx)\n", va);
while (len != 0) {
/*
* Check to see if we're mapping a range that could be
* mapped by a large page one page table level up. If so,
* use the larger page for efficiency:
*
* Long 64-bit mode: 2M PAGE = (AMD64_PAGESIZE << LEVEL_SHIFT)
* Legacy 32-bit mode: 4M PAGE = (AMD64_PAGESIZE << LEVEL_SHIFT)
*/
map_level--;
} else {
local_pagebits = 0;
}
level = 1;
idx_mask);
if (!(ENTRY_VALID(entry))) {
/*
* Grab an identity-mapped page at this
* level for an array of entries.
*/
/*
* Setup entry pointing to the new array
*/
/*
* Insert new entry into table
*/
/*
* If we're mapping in 64-bit long mode,
* make sure to identity map the
* allocation above into the 64-bit
* page tables to make sure the kernel
* can walk the 64-bit page tables.
*/
if (amd64_mmu_mode ==
}
/*
* Continue down another level.
*/
}
shift -= level_shift;
level++;
continue;
}
do {
/*
* Create mapping entry at this level.
*/
/*
* Install mapping entry
*/
shift + level_shift,
if (len != 0) {
/*
* We went over a parent's table entry mapping
* border, so we need to recalculate where we
* should be adding page tables.
*
* For example, if we are mapping 4K page
* tables in long mode, this means we crossed a
* 2M boundary. (It would be a 4M boundary for
* 32-bit legacy mode.)
*/
level = 1;
}
}
}
}
/*
* Save top of boot's 64-bit page tables for future use.
*/
/*
* Initialize long page tables
*/
{
extern int magic_phys;
int i;
/*
* Initialize long mode page tables.
*
* The only initial mappings are those for the identity mapped boot 4M
* (0x01000:0x400000) and those boot has already allocated.
*/
/*
* Preallocate enough level two and three entries to map the lower 4G
* of VA space, which will be reflected to the top 4G of VM space
* directly at the level two page tables.
*/
/* Identity map VA 0x200000:magic_phys at the PDE level via 2M pages */
/*
* Copy the balance of boot's initial mappings - this will fill in
* mapped entries in the page tables other than the 2M identity mapped
* page mentioned above.
*/
return (amd64_boot_pml4);
}