03831d35f7499c87d51205817c93e9a8d42c4baestevel/*
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER START
03831d35f7499c87d51205817c93e9a8d42c4baestevel *
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The contents of this file are subject to the terms of the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Common Development and Distribution License, Version 1.0 only
03831d35f7499c87d51205817c93e9a8d42c4baestevel * (the "License"). You may not use this file except in compliance
03831d35f7499c87d51205817c93e9a8d42c4baestevel * with the License.
03831d35f7499c87d51205817c93e9a8d42c4baestevel *
03831d35f7499c87d51205817c93e9a8d42c4baestevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
03831d35f7499c87d51205817c93e9a8d42c4baestevel * or http://www.opensolaris.org/os/licensing.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See the License for the specific language governing permissions
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and limitations under the License.
03831d35f7499c87d51205817c93e9a8d42c4baestevel *
03831d35f7499c87d51205817c93e9a8d42c4baestevel * When distributing Covered Code, include this CDDL HEADER in each
03831d35f7499c87d51205817c93e9a8d42c4baestevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If applicable, add the following below this CDDL HEADER, with the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * fields enclosed by brackets "[]" replaced with your own identifying
03831d35f7499c87d51205817c93e9a8d42c4baestevel * information: Portions Copyright [yyyy] [name of copyright owner]
03831d35f7499c87d51205817c93e9a8d42c4baestevel *
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER END
03831d35f7499c87d51205817c93e9a8d42c4baestevel */
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Copyright (c) 1999 by Sun Microsystems, Inc.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * All rights reserved.
03831d35f7499c87d51205817c93e9a8d42c4baestevel */
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel#ifndef _RESET_INFO_H
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define _RESET_INFO_H
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel#pragma ident "%Z%%M% %I% %E% SMI"
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel#ifdef __cplusplus
03831d35f7499c87d51205817c93e9a8d42c4baestevelextern "C" {
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*
03831d35f7499c87d51205817c93e9a8d42c4baestevel * All of the following data structures and defines come from sun4u server
03831d35f7499c87d51205817c93e9a8d42c4baestevel * POST. If the data in POST changes, then these structures must reflect
03831d35f7499c87d51205817c93e9a8d42c4baestevel * those changes.
03831d35f7499c87d51205817c93e9a8d42c4baestevel */
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel#include <sys/fhc.h> /* To get MAX_BOARDS constant */
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* BDA bit assignments */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BOARD_PRESENT (1<<0)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BOARD_OK (1<<1)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BOARD_TYPE_MSK (7<<2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BOARD_TYPE(x) (((x) & BOARD_TYPE_MSK) >> 2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* Board state mask and defines */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BD_STATE_MASK 0x3
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BD_LPM_FZN 0
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BD_ONLINE_FAIL 1
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BD_NOT_PRESENT 2
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define BD_ONLINE_NORMAL 3
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* define CPU 0 fields */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CPU0_PRESENT (1<<8)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CPU0_OK (1<<9)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CPU0_FAIL_CODE_MSK (7<<10)
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* define CPU 1 fields */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CPU1_PRESENT (1<<16)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CPU1_OK (1<<17)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CPU1_FAIL_CODE_MSK (7<<18)
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* supported board types */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CPU_TYPE 0
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define MEM_TYPE 1 /* CPU/MEM board with only memory */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define IO_TYPE1 2
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define IO_TYPE2 3
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define IO_TYPE3 4
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define IO_TYPE4 5 /* same as IO TYPE 1 but no HM or PHY chip */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CLOCK_TYPE 7
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* for CPU type UPA ports */
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel u_longlong_t afsr; /* Fault status register for CPU */
03831d35f7499c87d51205817c93e9a8d42c4baestevel u_longlong_t afar; /* Fault address register for CPU */
03831d35f7499c87d51205817c93e9a8d42c4baestevel} cpu_reset_state;
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* For the clock board */
03831d35f7499c87d51205817c93e9a8d42c4baesteveltypedef struct {
03831d35f7499c87d51205817c93e9a8d42c4baestevel unsigned long clk_ssr_1; /* reset status for the clock board */
03831d35f7499c87d51205817c93e9a8d42c4baestevel} clock_reset_state;
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevelstruct board_info {
03831d35f7499c87d51205817c93e9a8d42c4baestevel u_longlong_t board_desc;
03831d35f7499c87d51205817c93e9a8d42c4baestevel cpu_reset_state cpu[2]; /* could be a CPU */
03831d35f7499c87d51205817c93e9a8d42c4baestevel u_longlong_t ac_error_status;
03831d35f7499c87d51205817c93e9a8d42c4baestevel u_longlong_t dc_shadow_chain;
03831d35f7499c87d51205817c93e9a8d42c4baestevel uint_t fhc_csr;
03831d35f7499c87d51205817c93e9a8d42c4baestevel uint_t fhc_rcsr;
03831d35f7499c87d51205817c93e9a8d42c4baestevel};
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevelstruct reset_info {
03831d35f7499c87d51205817c93e9a8d42c4baestevel int length; /* size of the structure */
03831d35f7499c87d51205817c93e9a8d42c4baestevel int version; /* Version of the structure */
03831d35f7499c87d51205817c93e9a8d42c4baestevel struct board_info bd_reset_info[MAX_BOARDS];
03831d35f7499c87d51205817c93e9a8d42c4baestevel clock_reset_state clk; /* one clock board */
03831d35f7499c87d51205817c93e9a8d42c4baestevel unsigned char tod_timestamp[7];
03831d35f7499c87d51205817c93e9a8d42c4baestevel};
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel#ifdef __cplusplus
03831d35f7499c87d51205817c93e9a8d42c4baestevel}
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif
03831d35f7499c87d51205817c93e9a8d42c4baestevel
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* _RESET_INFO_H */