proc64_id.h revision 533d3a4910febc9985154b885dbe971e3c21ca04
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts * CDDL HEADER START
f0b8f6dd844f8752946b865bdd44175863b15812Peter Major * The contents of this file are subject to the terms of the
f0b8f6dd844f8752946b865bdd44175863b15812Peter Major * Common Development and Distribution License (the "License").
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts * You may not use this file except in compliance with the License.
f0b8f6dd844f8752946b865bdd44175863b15812Peter Major * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts * or http://www.opensolaris.org/os/licensing.
f0b8f6dd844f8752946b865bdd44175863b15812Peter Major * See the License for the specific language governing permissions
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c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts * information: Portions Copyright [yyyy] [name of copyright owner]
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c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts * Copyright (c) 2009, Intel Corporation
2d8eba3efb0ced5c2ab004e5b3e949094747aeb3jenkins * All rights reserved.
685810e390056c123842842f5104daa3179cf2c9Phill Cunnington * Portions Copyright 2009 Advanced Micro Devices, Inc.
685810e390056c123842842f5104daa3179cf2c9Phill Cunnington * Defines to determine what SSE instructions can be used for memops or strops
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#define NO_SSE 0x00 /* Default -- Don't use SSE instructions */
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#define USE_SSSE3 0x04 /* Supplemental SSE3 */
685810e390056c123842842f5104daa3179cf2c9Phill Cunnington#define USE_BSF 0x20 /* USE BSF class of instructions */
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts * Cache size defaults for Core 2 Duo
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#define INTEL_DFLT_L1_CACHE_SIZE (32 * 1024)
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#define INTEL_DFLT_L2_CACHE_SIZE (4 * 1024 * 1024)
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#define INTEL_DFLT_LARGEST_CACHE_SIZE (4 * 1024 * 1024)
bb788488efdd119f14e88ccc5a3cf302e743bcc4Phill Cunnington * Cache size defaults for AMD SledgeHammer
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#define AMD_DFLT_L2_CACHE_SIZE (1024 * 1024)
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpottsvoid __libc_get_cpuid(int cpuid_function, void *out_reg, int cache_index);
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpottsvoid __intel_set_memops_method(long sse_level);
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpottsvoid __set_cache_sizes(long l1_cache_size, long l2_cache_size,
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#endif /* _ASM */
c0202e5a338212ae386c672821f6dc4931c50f45James Phillpotts#endif /* _PROC64_ID_H */