controlregs.h revision 1b8adde7ba7d5e04395c141c5400dc2cffd7d809
/*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2006 Free Software Foundation, Inc.
*
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_CONTROLREGS_H
#define _SYS_CONTROLREGS_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file describes the x86 architecture control registers which
* are part of the privileged architecture.
*
* Many of these definitions are shared between IA-32-style and
* AMD64-style processors.
*/
/* CR0 Register */
/* XX64 eliminate these compatibility defines */
#define FMT_CR0 \
"\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
/* CR3 Register */
#define FMT_CR3 "\20\5pcd\4pwt"
/* CR4 Register */
#define FMT_CR4 \
"\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
/* Intel's SYSENTER configuration registers */
/* AMD's EFER register */
#define FMT_AMD_EFER \
"\20\14nxe\13lma\11lme\1sce"
/* AMD's SYSCFG register */
#define FMT_AMD_SYSCFG \
"\20\26tom2\25mvdm\24mfdm\23mfde"
/* AMD's FS.base and GS.base MSRs */
/* AMD's configuration MSRs, weakly documented in the revision guide */
#define MSR_AMD_DC_CFG 0xc0011022
/* AMD's HWCR MSR */
#define MSR_AMD_HWCR 0xc0010015
/* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
#define MSR_AMD_NB_CFG 0xc001001f
#define MSR_BU_CFG 0xc0011023
/* AMD */
#define MSR_AMD_PATCHLEVEL 0x8b
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_CONTROLREGS_H */