r8169.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/**************************************************************************
* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
* Written 2003 by Timothy Legge <tlegge@rogers.com>
*
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Portions of this code based on:
* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
* for Linux kernel 2.4.x.
*
* Written 2002 ShuChen <shuchen@realtek.com.tw>
* See Linux Driver for full information
*
* Linux Driver Version 1.27a, 10.02.2002
*
* Thanks to:
* Jean Chen of RealTek Semiconductor Corp. for
* providing the evaluation NIC used to develop
* this driver. RealTek's support for Etherboot
* is appreciated.
*
* REVISION HISTORY:
* ================
*
* v1.0 11-26-2003 timlegge Initial port of Linux driver
* v1.5 01-17-2004 timlegge Initial driver output cleanup
* v1.6 03-27-2004 timlegge Additional Cleanup
*
* Indent Options: indent -kr -i8
***************************************************************************/
/* to get some global routines like printf */
#include "etherboot.h"
/* to get the interface to the body of the program */
#include "nic.h"
/* to get the PCI support functions, if this is a PCI NIC */
#include "pci.h"
#include "timer.h"
#define drv_version "v1.6"
#define drv_date "03-27-2004"
typedef unsigned char u8;
typedef signed char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned int u32;
typedef signed int s32;
#define HZ 1000
#ifdef EDEBUG
#else
#define dprintf(x)
#endif
/* Condensed operations for readability. */
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/* media options
_10_Half = 0x01,
_10_Full = 0x02,
_100_Half = 0x04,
_100_Full = 0x08,
_1000_Full = 0x10,
*/
static int media = -1;
#if 0
/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
static int max_interrupt_work = 20;
#endif
#if 0
/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
The RTL chips use a 64 element hash table based on the Ethernet CRC. */
static int multicast_filter_limit = 32;
#endif
/* MAC address length*/
#define MAC_ADDR_LEN 6
/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
#define MAX_ETH_FRAME_SIZE 1536
#define RTL_MIN_IO_SIZE 0x80
enum RTL8169_registers {
MAC0 = 0, /* Ethernet hardware address. */
TxDescStartAddr = 0x20,
TxHDescStartAddr = 0x28,
FLASH = 0x30,
ERSR = 0x36,
ChipCmd = 0x37,
TxPoll = 0x38,
IntrMask = 0x3C,
IntrStatus = 0x3E,
TxConfig = 0x40,
RxConfig = 0x44,
RxMissed = 0x4C,
Cfg9346 = 0x50,
Config0 = 0x51,
Config1 = 0x52,
Config2 = 0x53,
Config3 = 0x54,
Config4 = 0x55,
Config5 = 0x56,
MultiIntr = 0x5C,
PHYAR = 0x60,
TBICSR = 0x64,
TBI_ANAR = 0x68,
TBI_LPAR = 0x6A,
PHYstatus = 0x6C,
RxMaxSize = 0xDA,
CPlusCmd = 0xE0,
RxDescStartAddr = 0xE4,
EarlyTxThres = 0xEC,
FuncEvent = 0xF0,
FuncEventMask = 0xF4,
FuncPresetState = 0xF8,
FuncForceEvent = 0xFC,
};
enum RTL8169_register_content {
/*InterruptStatusBits */
SYSErr = 0x8000,
PCSTimeout = 0x4000,
SWInt = 0x0100,
TxDescUnavail = 0x80,
RxFIFOOver = 0x40,
RxUnderrun = 0x20,
RxOverflow = 0x10,
TxErr = 0x08,
TxOK = 0x04,
RxErr = 0x02,
RxOK = 0x01,
/*RxStatusDesc */
RxRES = 0x00200000,
RxCRC = 0x00080000,
RxRUNT = 0x00100000,
RxRWT = 0x00400000,
/*ChipCmdBits */
CmdReset = 0x10,
CmdRxEnb = 0x08,
CmdTxEnb = 0x04,
RxBufEmpty = 0x01,
/*Cfg9346Bits */
Cfg9346_Lock = 0x00,
Cfg9346_Unlock = 0xC0,
/*rx_mode_bits */
AcceptErr = 0x20,
AcceptRunt = 0x10,
AcceptBroadcast = 0x08,
AcceptMulticast = 0x04,
AcceptMyPhys = 0x02,
AcceptAllPhys = 0x01,
/*RxConfigBits */
RxCfgFIFOShift = 13,
RxCfgDMAShift = 8,
/*TxConfigBits */
TxInterFrameGapShift = 24,
/*rtl8169_PHYstatus */
TBI_Enable = 0x80,
TxFlowCtrl = 0x40,
RxFlowCtrl = 0x20,
_1000bpsF = 0x10,
_100bps = 0x08,
_10bps = 0x04,
LinkStatus = 0x02,
FullDup = 0x01,
/*GIGABIT_PHY_registers */
PHY_CTRL_REG = 0,
PHY_STAT_REG = 1,
PHY_AUTO_NEGO_REG = 4,
PHY_1000_CTRL_REG = 9,
/*GIGABIT_PHY_REG_BIT */
PHY_Restart_Auto_Nego = 0x0200,
PHY_Enable_Auto_Nego = 0x1000,
/* PHY_STAT_REG = 1; */
PHY_Auto_Neco_Comp = 0x0020,
/* PHY_AUTO_NEGO_REG = 4; */
PHY_Cap_10_Half = 0x0020,
PHY_Cap_10_Full = 0x0040,
PHY_Cap_100_Half = 0x0080,
PHY_Cap_100_Full = 0x0100,
/* PHY_1000_CTRL_REG = 9; */
PHY_Cap_1000_Full = 0x0200,
PHY_Cap_Null = 0x0,
/*_MediaType*/
_10_Half = 0x01,
_10_Full = 0x02,
_100_Half = 0x04,
_100_Full = 0x08,
_1000_Full = 0x10,
/*_TBICSRBit*/
TBILinkOK = 0x02000000,
};
static struct {
const char *name;
} rtl_chip_info[] = {
{
"RTL-8169", 0x00, 0xff7e1880,},};
enum _DescStatusBit {
OWNbit = 0x80000000,
EORbit = 0x40000000,
FSbit = 0x20000000,
LSbit = 0x10000000,
};
struct TxDesc {
};
struct RxDesc {
};
/* The descriptors for this card are required to be aligned on
256 byte boundaries. As the align attribute does not do more than
16 bytes of alignment it requires some extra steps. Add 256 to the
size of the array and the init_ring adjusts the alignment */
/* Define the TX Descriptor */
/* Create a static buffer of size RX_BUF_SZ for each
TX Descriptor. All descriptors point to a
part of this buffer */
/* Define the RX Descriptor */
/* Create a static buffer of size RX_BUF_SZ for each
RX Descriptor All descriptors point to a
part of this buffer */
struct rtl8169_private {
void *mmio_addr; /* memory map physical address */
int chipset;
unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
unsigned char *Tx_skbuff[NUM_TX_DESC];
} tpx;
static struct rtl8169_private *tpc;
static const u16 rtl8169_intr_mask =
static const unsigned int rtl8169_rx_config =
{
int i;
udelay(1000);
for (i = 2000; i > 0; i--) {
/* Check if the RTL8169 has completed writing to the specified MII register */
break;
} else {
udelay(100);
}
}
}
{
int i, value = -1;
udelay(1000);
for (i = 2000; i > 0; i--) {
/* Check if the RTL8169 has completed retrieving data from the specified MII register */
break;
} else {
udelay(100);
}
}
return value;
}
{
int i;
unsigned long rtreg_base, rtreg_len;
if (rtreg_len < RTL_MIN_IO_SIZE) {
printf("Invalid PCI region size(s), aborting\n");
}
/* pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); */
/* ioremap MMIO region */
if (ioaddr == 0)
return 0;
/* Soft reset the chip. */
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--)
break;
else
udelay(10);
/* identify chip attached to board */
goto match;
}
/* if unknown chip, assume array element #0, original RTL-8169 in this case */
dprintf(("PCI device: unknown chip version, assuming RTL-8169\n"));
dprintf(("PCI device: TxConfig = 0x%hX\n",
return 1;
return 0;
}
/**************************************************************************
IRQ - Wait for a frame
***************************************************************************/
int intr_status = 0;
switch ( action ) {
case DISABLE:
case ENABLE:
/* h/w no longer present (hotplug?) or major error,
bail */
if (intr_status == 0xFFFF)
break;
break;
case FORCE :
break;
}
}
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
int cur_rx;
unsigned int intr_status = 0;
/* There is a packet ready */
if(!retreive)
return 1;
/* h/w no longer present (hotplug?) or major error,
bail */
if (intr_status == 0xFFFF)
return 0;
else
} else
printf("Error Rx");
/* FIXME: shouldn't I reset the status on an error */
return 1;
}
/* FIXME: There is no reason to do this as cur_rx did not change */
return (0); /* initially as this is called to flush the input */
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
unsigned int t, /* Type */
unsigned int s, /* size */
const char *p)
{ /* Packet */
/* send the packet to destination */
/* point to the current txb incase multiple tx_rings are used */
s += ETH_HLEN;
s &= 0x0FFF;
while (s < ETH_ZLEN)
ptxb[s++] = '\0';
ETH_ZLEN);
else
: ETH_ZLEN);
printf("TX Time Out");
}
}
{
int rx_mode;
/* IFF_ALLMULTI */
/* Too many to filter perfectly -- accept all multicasts. */
tmp =
}
{
u32 i;
/* Soft reset the chip. */
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--) {
break;
else
udelay(10);
}
/* For gigabit rtl8169 */
/* Set Rx Config register */
/* Set DMA burst size and Interframe Gap Time */
udelay(10);
/* no early-rx interrupts */
}
{
int i;
for (i = 0; i < NUM_TX_DESC; i++) {
}
for (i = 0; i < NUM_RX_DESC; i++) {
if (i == (NUM_RX_DESC - 1))
else
}
}
/**************************************************************************
RESET - Finish setting up the ethernet interface
***************************************************************************/
{
int i;
if (tpc->TxDescArrays == 0)
printf("Allot Error");
/* Tx Desscriptor needs 256 bytes alignment; */
/* Rx Desscriptor needs 256 bytes alignment; */
printf("Allocate RxDescArray or TxDescArray failed\n");
return;
}
/* Construct a perfect filter frame with the mac address as first match
* and broadcast for all others */
for (i = 0; i < 192; i++)
txb[i] = 0xFF;
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
{
int i;
/* Stop the chip's Tx and Rx DMA processes. */
/* Disable interrupts by clearing the interrupt mask. */
for (i = 0; i < NUM_RX_DESC; i++) {
}
}
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
***************************************************************************/
#define board_found 1
#define valid_link 0
{
static int board_idx = -1;
static int printed_version = 0;
int i, rc;
board_idx++;
printed_version = 1;
/* point to private storage */
/* Get MAC address. FIXME: read EEPROM */
for (i = 0; i < MAC_ADDR_LEN; i++)
/* Print out some hardware info */
ioaddr);
/* if TBI is not endbled */
if (option > 0) {
printf(" Force-mode Enabled.\n");
switch (option) {
case _10_Half:
break;
case _10_Full:
break;
case _100_Half:
break;
case _100_Full:
break;
case _1000_Full:
break;
default:
break;
}
/* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
} else {
dprintf(("Auto-negotiation Enabled.\n",
(val & 0x1F));
/* enable 1000 Full Mode */
}
/* Enable auto-negotiation and restart auto-nigotiation */
udelay(100);
/* wait for auto-negotiation process */
for (i = 10000; i > 0; i--) {
/* Check if auto-negotiation complete */
udelay(100);
("1000Mbps Full-duplex operation.\n");
} else {
("%sMbps %s-duplex operation.\n",
"10",
"Half");
}
break;
} else {
udelay(100);
}
} /* end for-loop to wait for auto-negotiation process */
} else {
udelay(100);
("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
}
/* point to NIC specific routines */
return 1;
}
static struct pci_id r8169_nics[] = {
};
struct pci_driver r8169_driver = {
.type = NIC_DRIVER,
.probe = r8169_probe,
.ids = r8169_nics,
.class = 0,
};