forcedeth.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/**************************************************************************
* forcedeth.c -- Etherboot device driver for the NVIDIA nForce
* media access controllers.
*
* Note: This driver is based on the Linux driver that was based on
* a cleanroom reimplementation which was based on reverse
* engineered documentation written by Carl-Daniel Hailfinger
* and Andrew de Quincey. It's neither supported nor endorsed
* by NVIDIA Corp. Use at your own risk.
*
* Written 2004 by Timothy Legge <tlegge@rogers.com>
*
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Portions of this code based on:
* forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
*
* (C) 2003 Manfred Spraul
* See Linux Driver for full information
*
* Linux Driver Version 0.22, 19 Jan 2004
*
*
* REVISION HISTORY:
* ================
* v1.0 01-31-2004 timlegge Initial port of Linux driver
* v1.1 02-03-2004 timlegge Large Clean up, first release
*
* Indent Options: indent -kr -i8
***************************************************************************/
/* to get some global routines like printf */
#include "etherboot.h"
/* to get the interface to the body of the program */
#include "nic.h"
/* to get the PCI support functions, if this is a PCI NIC */
#include "pci.h"
/* Include timer support functions */
#include "timer.h"
#define drv_version "v1.1"
#define drv_date "02-03-2004"
//#define TFTM_DEBUG
#ifdef TFTM_DEBUG
#else
#define dprintf(x)
#endif
typedef unsigned char u8;
typedef signed char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned int u32;
typedef signed int s32;
/* Condensed operations for readability. */
unsigned long BASE;
/* NIC specific static variables go here */
/*
* Hardware access:
*/
#define DEV_NEED_LASTPACKET1 0x0001
#define DEV_IRQMASK_1 0x0002
#define DEV_IRQMASK_2 0x0004
#define DEV_NEED_TIMERIRQ 0x0008
enum {
NvRegIrqStatus = 0x000,
#define NVREG_IRQSTAT_MIIEVENT 0040
#define NVREG_IRQSTAT_MASK 0x1ff
NvRegIrqMask = 0x004,
#define NVREG_IRQ_RX 0x0002
#define NVREG_IRQ_RX_NOBUF 0x0004
#define NVREG_IRQ_TX_ERR 0x0008
#define NVREG_IRQ_TX2 0x0010
#define NVREG_IRQ_TIMER 0x0020
#define NVREG_IRQ_LINK 0x0040
#define NVREG_IRQ_TX1 0x0100
#define NVREG_IRQMASK_WANTED_1 0x005f
#define NVREG_IRQMASK_WANTED_2 0x0147
#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
NvRegUnknownSetupReg6 = 0x008,
#define NVREG_UNKSETUP6_VAL 3
/*
* NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
* NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
*/
NvRegPollingInterval = 0x00c,
#define NVREG_POLL_DEFAULT 970
NvRegMisc1 = 0x080,
#define NVREG_MISC1_HD 0x02
#define NVREG_MISC1_FORCE 0x3b0f3c
NvRegTransmitterControl = 0x084,
#define NVREG_XMITCTL_START 0x01
NvRegTransmitterStatus = 0x088,
#define NVREG_XMITSTAT_BUSY 0x01
NvRegPacketFilterFlags = 0x8c,
#define NVREG_PFF_ALWAYS 0x7F0008
#define NVREG_PFF_PROMISC 0x80
#define NVREG_PFF_MYADDR 0x20
NvRegOffloadConfig = 0x90,
#define NVREG_OFFLOAD_HOMEPHY 0x601
#define NVREG_OFFLOAD_NORMAL 0x5ee
NvRegReceiverControl = 0x094,
#define NVREG_RCVCTL_START 0x01
NvRegReceiverStatus = 0x98,
#define NVREG_RCVSTAT_BUSY 0x01
NvRegRandomSeed = 0x9c,
#define NVREG_RNDSEED_MASK 0x00ff
#define NVREG_RNDSEED_FORCE 0x7f00
NvRegUnknownSetupReg1 = 0xA0,
#define NVREG_UNKSETUP1_VAL 0x16070f
NvRegUnknownSetupReg2 = 0xA4,
#define NVREG_UNKSETUP2_VAL 0x16
NvRegMacAddrA = 0xA8,
NvRegMacAddrB = 0xAC,
NvRegMulticastAddrA = 0xB0,
#define NVREG_MCASTADDRA_FORCE 0x01
NvRegMulticastAddrB = 0xB4,
NvRegMulticastMaskA = 0xB8,
NvRegMulticastMaskB = 0xBC,
NvRegTxRingPhysAddr = 0x100,
NvRegRxRingPhysAddr = 0x104,
NvRegRingSizes = 0x108,
#define NVREG_RINGSZ_TXSHIFT 0
#define NVREG_RINGSZ_RXSHIFT 16
NvRegUnknownTransmitterReg = 0x10c,
NvRegLinkSpeed = 0x110,
#define NVREG_LINKSPEED_FORCE 0x10000
#define NVREG_LINKSPEED_10 10
#define NVREG_LINKSPEED_100 100
#define NVREG_LINKSPEED_1000 1000
NvRegUnknownSetupReg5 = 0x130,
NvRegUnknownSetupReg3 = 0x134,
#define NVREG_UNKSETUP3_VAL1 0x200010
NvRegTxRxControl = 0x144,
#define NVREG_TXRXCTL_KICK 0x0001
#define NVREG_TXRXCTL_BIT1 0x0002
#define NVREG_TXRXCTL_BIT2 0x0004
#define NVREG_TXRXCTL_IDLE 0x0008
#define NVREG_TXRXCTL_RESET 0x0010
NvRegMIIStatus = 0x180,
#define NVREG_MIISTAT_ERROR 0x0001
#define NVREG_MIISTAT_LINKCHANGE 0x0008
#define NVREG_MIISTAT_MASK 0x000f
#define NVREG_MIISTAT_MASK2 0x000f
NvRegUnknownSetupReg4 = 0x184,
#define NVREG_UNKSETUP4_VAL 8
NvRegAdapterControl = 0x188,
#define NVREG_ADAPTCTL_START 0x02
#define NVREG_ADAPTCTL_LINKUP 0x04
#define NVREG_ADAPTCTL_PHYVALID 0x4000
#define NVREG_ADAPTCTL_RUNNING 0x100000
#define NVREG_ADAPTCTL_PHYSHIFT 24
NvRegMIISpeed = 0x18c,
#define NVREG_MIIDELAY 5
NvRegMIIControl = 0x190,
#define NVREG_MIICTL_INUSE 0x10000
#define NVREG_MIICTL_WRITE 0x08000
#define NVREG_MIICTL_ADDRSHIFT 5
NvRegMIIData = 0x194,
NvRegWakeUpFlags = 0x200,
#define NVREG_WAKEUPFLAGS_VAL 0x7770
#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
#define NVREG_WAKEUPFLAGS_D3SHIFT 12
#define NVREG_WAKEUPFLAGS_D2SHIFT 8
#define NVREG_WAKEUPFLAGS_D1SHIFT 4
#define NVREG_WAKEUPFLAGS_D0SHIFT 0
#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
NvRegPatternCRC = 0x204,
NvRegPatternMask = 0x208,
NvRegPowerCap = 0x268,
NvRegPowerState = 0x26c,
#define NVREG_POWERSTATE_POWEREDUP 0x8000
#define NVREG_POWERSTATE_VALID 0x0100
#define NVREG_POWERSTATE_MASK 0x0003
#define NVREG_POWERSTATE_D0 0x0000
#define NVREG_POWERSTATE_D1 0x0001
#define NVREG_POWERSTATE_D2 0x0002
#define NVREG_POWERSTATE_D3 0x0003
};
#define NV_TX_LASTPACKET (1<<0)
#define NV_RX_DESCRIPTORVALID (1<<0)
/* Miscelaneous hardware related defines: */
#define NV_PCI_REGSZ 0x270
/* various timeout delays: all in usec */
#define NV_TXRX_RESET_DELAY 4
#define NV_TXSTOP_DELAY1 10
#define NV_TXSTOP_DELAY1MAX 500000
#define NV_TXSTOP_DELAY2 100
#define NV_RXSTOP_DELAY1 10
#define NV_RXSTOP_DELAY1MAX 500000
#define NV_RXSTOP_DELAY2 100
#define NV_SETUP5_DELAY 5
#define NV_SETUP5_DELAYMAX 50000
#define NV_POWERUP_DELAY 5
#define NV_POWERUP_DELAYMAX 5000
#define NV_MIIBUSY_DELAY 50
#define NV_MIIPHY_DELAY 10
#define NV_MIIPHY_DELAYMAX 10000
#define NV_WAKEUPPATTERNS 5
#define NV_WAKEUPMASKENTRIES 4
/* General driver defaults */
#define RX_RING 4
#define TX_RING 2
/* limited to 1 packet until we understand NV_TX_LASTPACKET */
#define TX_LIMIT_STOP 10
#define TX_LIMIT_START 5
/* even more slack */
struct ring_desc {
};
/* Define the TX Descriptor */
/* Create a static buffer of size RX_BUF_SZ for each
TX Descriptor. All descriptors point to a
part of this buffer */
/* Define the TX Descriptor */
/* Create a static buffer of size RX_BUF_SZ for each
RX Descriptor All descriptors point to a
part of this buffer */
/* Private Storage for the NIC */
struct forcedeth_private {
/* General data:
* Locking: spin_lock(&np->lock); */
int in_shutdown;
int duplex;
int phyaddr;
/* General data: RO fields */
/* rx specific fields.
* Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
*/
unsigned int rx_buf_sz;
/*
* tx specific fields.
*/
} npx;
static struct forcedeth_private *np;
{
/* force out pending posted writes */
}
{
do {
if (delaymax < 0) {
if (msg)
return 1;
}
return 0;
}
#define MII_READ (-1)
/* Link partner ability register. */
*
* Caller must guarantee serialization
*/
int value)
{
int was_running;
int retval;
was_running = 0;
if (reg & NVREG_ADAPTCTL_RUNNING) {
was_running = 1;
}
if (reg & NVREG_MIICTL_INUSE) {
}
reg =
}
dprintf(("mii_rw of reg %d at PHY %d timed out.\n",
retval = -1;
/* it was a write operation - fewer failures are detectable */
dprintf(("mii_rw wrote 0x%x to reg %d at PHY %d\n",
retval = 0;
dprintf(("mii_rw of reg %d at PHY %d failed.\n",
retval = -1;
} else {
/* FIXME: why is that required? */
udelay(50);
dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n",
}
if (was_running) {
}
return retval;
}
{
dprintf(("start_rx\n"));
/* Already running? Stop it. */
}
}
static void stop_rx(void)
{
dprintf(("stop_rx\n"));
"stop_rx: ReceiverStatus remained busy");
}
{
dprintf(("start_tx\n"));
}
static void stop_tx(void)
{
dprintf(("stop_tx\n"));
"stop_tx: TransmitterStatus remained busy");
}
{
dprintf(("txrx_reset\n"));
base + NvRegTxRxControl);
}
/*
* alloc_rx: fill rx ring entries.
* Return 1 if the allocations for the skbs failed and the
* rx engine is without Available descriptors
*/
{
int i;
//while (np->cur_rx != refill_rx) {
for (i = 0; i < RX_RING; i++) {
//int nr = refill_rx % RX_RING;
rx_ring[i].PacketBuffer =
wmb();
/* printf("alloc_rx: Packet %d marked as Available\n",
refill_rx); */
refill_rx++;
}
return 1;
return 0;
}
{
dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n",
/* FIXME: handle parallel detection properly, handle gigabit ethernet */
if (lpa & LPA_100FULL) {
newdup = 1;
} else if (lpa & LPA_100HALF) {
newdup = 0;
} else if (lpa & LPA_10FULL) {
newdup = 1;
} else if (lpa & LPA_10HALF) {
newdup = 0;
} else {
newdup = 0;
}
return 1;
}
return 0;
}
{
int i;
for (i = 0; i < TX_RING; i++) {
}
for (i = 0; i < RX_RING; i++) {
}
}
{
addr[0] |= NVREG_MCASTADDRA_FORCE;
pff |= NVREG_PFF_ALWAYS;
stop_rx();
}
/**************************************************************************
RESET - Reset the NIC to prepare for use
***************************************************************************/
{
ret = 0;
dprintf(("forcedeth: open\n"));
/* 1) erase previous misconfiguration */
/* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
/* 2) initialize descriptor rings */
np->in_shutdown = 0;
/* 3) set mac address */
{
mac[0] =
mac[1] =
}
/* 4) continue setup */
"open: SetupReg5, Bit 31 remained off\n");
/* 5) Find a suitable PHY */
for (i = 1; i < 32; i++) {
if (id1 < 0)
continue;
if (id2 < 0)
continue;
dprintf(("open: Found PHY %04x:%04x at address %d.\n",
break;
}
if (i == 32) {
printf("open: failing due to lack of suitable PHY.\n");
ret = -1;
goto out_drain;
}
printf("%d-Mbs Link, %s-Duplex\n",
/* 6) continue setup */
base + NvRegMisc1);
/* FIXME: I cheated and used the calculator to get a random number */
i = 75963081;
base + NvRegRandomSeed);
/* 7) start packet processing */
base + NvRegRingSizes);
if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) {
base + NvRegPowerState);
}
udelay(10);
base + NvRegPowerState);
/*
writel(np->irqmask, base + NvRegIrqMask);
*/
//start_rx(nic);
if (!
printf("no link during initialization.\n");
}
udelay(10000);
return ret;
}
//extern void hex_dump(const char *data, const unsigned int len);
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
int len;
int i;
return 0;
}
if ( ! retrieve ) return 1;
/* got a valid packet - forward it to the network core */
//hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
wmb();
return 1;
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
unsigned int t, /* Type */
unsigned int s, /* size */
const char *p)
{ /* Packet */
/* send the packet to destination */
//u16 status;
/* point to the current txb incase multiple tx_rings are used */
//np->tx_skbuff[nr] = ptxb;
/* copy the packet to ring buffer */
s += ETH_HLEN;
while (s < ETH_ZLEN) /* pad to min length */
ptxb[s++] = '\0';
wmb();
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
{
/* put the card in its initial state */
/* This function serves 3 purposes.
* This disables DMA and interrupts so we don't receive
* unexpected packets or interrupts from the card after
* etherboot has finished.
* This frees resources so etherboot may use
* this driver on another interface
* This allows etherboot to reinitialize the interface
* if something is something goes wrong.
*/
stop_tx();
stop_rx();
/* disable interrupts on the nic or we will lock up */
dprintf(("Irqmask is zero again\n"));
/* specia op:o write back the misordered MAC address - otherwise
* the next probe_nic would see a wrong address.
*/
}
/**************************************************************************
IRQ - Enable, Disable, or Force interrupts
***************************************************************************/
{
switch ( action ) {
case DISABLE :
break;
case ENABLE :
break;
case FORCE :
break;
}
}
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
***************************************************************************/
#define IORESOURCE_MEM 0x00000200
#define board_found 1
#define valid_link 0
{
unsigned long addr;
int sz;
return 0;
printf("forcedeth.c: Found %s, vendor=0x%hX, device=0x%hX\n",
/* point to private storage */
/* BASE is used throughout to address the card */
if (!BASE)
return 0;
//rx_ring[0] = rx_ring;
//tx_ring[0] = tx_ring;
/* read the mac address */
#ifdef LINUX
/*
* Bad mac address. At least one bios sets the mac address
* to 01:23:45:67:89:ab
*/
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
"Please complain to your hardware vendor. Switching to a random MAC.\n");
}
#endif
case 0x01C3: // nforce
break;
case 0x0066: // nforce2
break;
case 0x00D6: // nforce3
}
dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n",
// if (board_found && valid_link)
/* point to NIC specific routines */
return 1;
// }
/* else */
}
static struct pci_id forcedeth_nics[] = {
};
struct pci_driver forcedeth_driver = {
.type = NIC_DRIVER,
.name = "forcedeth",
.probe = forcedeth_probe,
.ids = forcedeth_nics,
.class = 0,
};