mcamd_rowcol_impl.h revision 7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fe
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/*
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7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * CDDL HEADER END
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi *
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Use is subject to license terms.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#ifndef _MCAMD_ROWCOL_IMPL_H
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define _MCAMD_ROWCOL_IMPL_H
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#pragma ident "%Z%%M% %I% %E% SMI"
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#include <mcamd_api.h>
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#include <sys/mc_amd.h>
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#ifdef __cplusplus
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiextern "C" {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#endif
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_PC_COLADDRBIT 10 /* col address bit used for precharge */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_PC_ALL -1 /* marker used in tables */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_CS_SCALE (1024 * 1024)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_CS_SIZE(bam, width) \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi ((size_t)bam->bam_sizemb * MC_CS_SCALE * ((width) == 128 ? 2 : 1))
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_CS_MODE(csbmap, csnum) \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi (csbmap >> MC_CHIP_DIMMPAIR(csnum) * MC_DC_BAM_CSBANK_SHIFT & \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi MC_DC_BAM_CSBANK_MASK)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define BIT(val, num) ((val) & 1ULL << num)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define BITS(val, high, low) \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi ((val) & (((2ULL << (high)) - 1) & ~((1ULL << (low)) - 1)))
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define SETBIT(var, num) (var |= (1ULL << (num)))
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define BITVAL(var, num) ((BIT(var, num) >> (num)) & 1ULL)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_RC_ROW_MAX 14 /* maximum number of row address bits */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_RC_COL_MAX 12 /* maximum number of col address bits */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_RC_BANKBITS 2 /* number of internal banksel bits */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_RC_BANKARGS 3 /* bits used for 1 banksel bit */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_RC_CSMODES 16 /* max number of cs bankaddr modes */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/*
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Row, column and bank mapping is derived after allowing for interleave
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * from the normalized dram address through the tables of BKDG 3.29
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * section 3.5.6.1. We have tables for:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi *
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * . rev CG and earlier, 64-bit MC mode
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * . rev CG and earlier, 128-bit MC mode
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * . rev D and later, 64-bit MC mode (no bank swizzling if rev E)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * . rev D and later, 128-bit MC mode (no bank swizzling if rev E)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * . rev E and later, 64-bit MC mode with bank swizzling
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * . rev E and later, 128-bit MC mode with bank swizzling
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi *
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Each table is indexed by CS Mode (equivalently, CS size) and tells us
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * which bits of the normalized dram address (i.e., the address modified for
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * the local MC base address and with node interleave selection bits removed)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * to use in forming the column address, row address and internal bank
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * selection.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi *
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Note that for rev CG and earlier there is some overloading of CS mode
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * encoding such that we do not know the number of row and column address
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * bits from the CS mode alone, e.g., for 128MB DIMM modules we may have
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * 13 row bits and 9 column, or 12 row and 10 column. In these case the
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * tables held in the structures defined below will have a duplicated bit
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * number in the row and column bits. In these ambiguous cases cm_rc_ambig
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * should be set in the table.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindistruct bankaddr_mode {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int bam_sizemb; /* DIMM size in MB */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int bam_nrows; /* number of row address bits */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int bam_ncols; /* number of column address bits */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int bam_ambig; /* numbers are maximums; keep last */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi};
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindistruct csrcb_map {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int csrcb_bankargs[MC_RC_BANKBITS][MC_RC_BANKARGS];
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int csrcb_rowbits[MC_RC_ROW_MAX];
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int csrcb_colbits[MC_RC_COL_MAX + 1]; /* one for MC_PC_ALL */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi};
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindistruct csrcb_map_tbl {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int mt_rev; /* revision to which this applies */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int mt_width; /* MC mode (64 or 128) */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi struct csrcb_map mt_csmap[MC_RC_CSMODES];
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi};
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindistruct csintlv_desc {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int csi_factor; /* cs interleave factor */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int csi_hibit; /* first non-offset bit in addr */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int csi_lobit; /* first row bit in addr */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi int csi_nbits; /* number of bits to swap in mask */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi};
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_RC_CSI_SWAPPED_BIT(csidp, n) \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi (csidp->csi_factor && n >= csidp->csi_lobit && \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi n <= csidp->csi_lobit + csidp->csi_nbits - 1)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define MC_RC_CSI_BITSWAP(csidp, n) \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi (csidp->csi_hibit + n - csidp->csi_lobit)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiextern const struct bankaddr_mode *rct_bankaddr_mode(uint_t, uint_t);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiextern const struct csrcb_map *rct_rcbmap(uint_t, int, uint_t);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiextern void rct_csintlv_bits(uint_t, int, uint_t, int, struct csintlv_desc *);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#ifdef __cplusplus
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi}
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#endif
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#endif /* _MCAMD_ROWCOL_IMPL_H */