system-board.info revision 36e5aa2ab5c51d4747a2470e41ccb782056c90e7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* ident "%Z%%M% %I% %E% SMI"
*
* This file creates the system board structure
*/
/*
* define a macro to force a #ident line into the output stream
* otherwise cpp removes it. Use #ifndef because of #included definitions.
*/
id("%Z%%M% %I% %E% SMI")
/*
* motherboard seeprom source
*/
PROP FRUDataAvailable void r
/*
* RMC Board Seeprom Source
*/
PROP FRUDataAvailable void r
/*
* FIOB Board Seeprom Source
*/
PROP FRUDataAvailable void r
/*
*/
PROP FRUDataAvailable void r
/*
* HDDBP Board Seeprom Source and fru parent
*/
PROP FRUDataAvailable void r
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/HDDCNTRL/disk-controller/HDDBP/disk-backplane-8
/*
* HDDCNTRL Board Seeprom Source
*
* Note: see piclfrutree.info for fruid prom info
*/
/*
* Proccessor Board 0
*/
PROP FRUDataAvailable void r
/*
* Proccessor Board 1
*/
PROP FRUDataAvailable void r
/*
* Proccessor Board 2
*/
PROP FRUDataAvailable void r
/*
* Proccessor Board 3
*/
PROP FRUDataAvailable void r
/*
* Processors
*/
/************************************
* CPU Board 0 Processor 0
************************************/
/************************************
* CPU Board 1 Processor 0
************************************/
/************************************
* CPU Board 2 Processor 0
************************************/
/************************************
* CPU Board 3 Processor 0
************************************/
/************************************
* CPU Board 0 Processor 0 memory
************************************/
/************************************
* CPU Board 1 Processor 0 memory
************************************/
/************************************
* CPU Board 2 Processor 0 memory
************************************/
/************************************
* CPU Board 3 Processor 0 memory
************************************/
/************************************
* Dimm nodes
************************************/
/*
* Board 0 CPU 0
*/
/*
* Board 1 CPU 0
*/
/*
* Board 2 CPU 0
*/
/*
* Board 3 CPU 0
*/
/*********************************************
* DIMM seeprom sources and operational status
*********************************************/
/* Fill in a status of "ok" for all possible dimms in the platform
* tree. This status may be overridden by ASR with "disabled" or "unused".
* actually get created.
*/
/*
* Board 0 CPU 0
*/
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
/*
* Board 1 CPU 0
*/
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
/*
* Board 2 CPU 0
*/
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
/*
* Board 3 CPU 0
*/
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
PROP FRUDataAvailable void r
/************************************
* DIMM FRU parents
***********************************/
/*
* Board 0 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B1/bank/D1/mem-module
/*
* Board 1 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B1/bank/D1/mem-module
/*
* Board 2 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B1/bank/D1/mem-module
/*
* Board 3 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B1/bank/D1/mem-module
/************************************
* DIMM parents
***********************************/
/*
* Board 0 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C0/cpu-module/P0/cpu/B1/bank/D1/mem-module
/*
* Board 1 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C1/cpu-module/P0/cpu/B1/bank/D1/mem-module
/*
* Board 2 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C2/cpu-module/P0/cpu/B1/bank/D1/mem-module
/*
* Board 3 CPU 0
*/
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B0/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B0/bank/D1/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B1/bank/D0/mem-module
REFPROP _fru_parent name:/frutree/chassis/MB/system-board/C3/cpu-module/P0/cpu/B1/bank/D1/mem-module
/*
* create reference properties for motherboard pci devices
*/