fsr_test.s revision 60c45ed01d4f99571d468c42f609d11a099fab1e
/*
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*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
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*/
/*
* Copyright 2008 Sun Microsystems, Inc.
* All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Assembly routines used in the FSR testing.
*/
/*
* DCTI couple for instruction picking
* ===================================
*
* The routines fcmps_fcc() and fcmpd_fcc() use a DCTI couple
* for choosing a specific instruction from a set of instructions.
* DCTI : Delayed Control Transfer Instruction. A DCTI couple
* contains a control transfer instruction in the delay slot of
* another control transfer instruction and the entire setup
* looks something like this :
*
* jmp <tgt1>
* ba <tgt2>
*
* . . .
*
* table : ! Table of instructions. tgt1 will be pointing
* ! to one of the instructions in it.
*
* . . .
*
* tgt2 :
* . . .
*
* This functionality is explained below using the value of PC and
* nPC. We start with the jmp instruction.
*
* step1 : PC='jmp' nPC='ba'
* step2 : PC='ba' nPC='tgt1' ! jmp changes the nPC
* step3 : PC='tgt1' nPC='tgt2' ! ba changes the nPC
* step4 : PC='tgt2' nPC=...
*
*/
# include <sys/asm_linkage.h>
/*
* uint64_t res_fsr = fcmps_fcc(unsigned int val1, unsigned int val2,
* unsigned int fcc);
*
* Single-precision FP comparision.
*
* Operand 'fcc' indicates which fcc field of FSR to use.
*/
.data
fcmps_opr1 : .word 0
fcmps_opr2 : .word 0
fcmps_result : .word 0,0
fccn1 :
fini :
/*
* uint64_t res_fsr = fcmpd_fcc(uint64_t val1, uint64_t val2,
* unsigned int fcc);
*
* Double-precision FP comparision.
*
* Operand 'fcc' indicates which fcc field of FSR to use.
*
* In SPARC V8, uint64_t parameters are split and stored in
* consecutive registers. For example, the first uint64_t
* parameter of the function will be stored in %i0 and %i1.
* This is not done in SPARC V9 as the registers are 64-bit.
*/
.data
.align 8
fcmpd_opr1 : .word 0,0
fcmpd_opr2 : .word 0,0
fcmpd_result : .word 0,0
fccn2 :
egress :