cmd_cpu.h revision 6dfee4834394825da35b977ca71cdc965bc7b6a4
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _CMD_CPU_H
#define _CMD_CPU_H
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Each CPU of interest has a cmd_cpu_t structure. CPUs become of interest when
* they are the focus of ereports, or when they detect UEs. CPUs may be the
* target of several different kinds of ereport, each of which is tracked
* differently. cpu_cases lists the types of cases that can be open against a
* given CPU. The life of a CPU is complicated by the fact that xxCs and xxUs
* received by the DE may in fact be side-effects of earlier UEs, xxCs, or xxUs.
* Causes of side-effects, and actions taken to resolve them, can be found below
* and in cmd_memerr.h.
*
* Data structures:
* ________ CMD_PTR_CPU_ICACHE
* / \ ,--------. CMD_PTR_CPU_DCACHE
* |CPU | <---- |case_ptr| (one or more of CMD_PTR_CPU_PCACHE )
* | | `--------' CMD_PTR_CPU_ITLB
* |,-------| ,-------. CMD_PTR_CPU_DTLB
* ||asru | ----> |fmri_t | CMD_PTR_CPU_L2DATA
* |:-------| :-------: CMD_PTR_CPU_L2DATA_UERETRY
* ||fru | ----> |fmri_t | CMD_PTR_CPU_L2TAG
* |`-------| `-------' CMD_PTR_CPU_L3DATA
* | | ,---------. CMD_PTR_CPU_L3DATA_UERETRY
* | uec | ----> |UE cache | CMD_PTR_CPU_L3TAG
* \________/ `---------' CMD_PTR_CPU_FPU
* CMD_PTR_CPU_IREG
* CMD_PTR_CPU_FREG
* CMD_PTR_CPU_MAU
* CMD_PTR_CPU_L2CTL
*
* ________
* / \ ,--------.
* | xr | <---- |case_ptr| (CMD_PTR_XR_WAITER)
* | | `--------'
* |,-------| ,-------.
* ||rsrc | ----> |fmri_t |
* |`-------| `-------'
* | cpu | ----> detecting CPU
* \________/
*
* Data structure P? Case- Notes
* Rel?
* ---------------- --- ----- --------------------------------------
* cmd_cpu_t Yes No Name is derived from CPU ID ("cpu_%d")
* cmd_case_ptr_t Yes Yes Name is case's UUID
* cpu_asru (fmri_t) Yes No Name is derived from CPU ID ("cpu_asru_%d")
* cpu_fru (fmri_t) Yes No Name is derived from CPU ID ("cpu_fru_%d")
* cpu_uec Yes No Name is derived from CPU ID ("cpu_uec_%d")
* cmd_xr_t Yes Yes Name is `redelivery'
* xr_rsrc (fmri_t) Yes No Name is derived from case's UUID ("%s_rsrc")
*/
#include <cmd.h>
#include <cmd_state.h>
#include <cmd_fmri.h>
#ifdef sun4u
#include <sys/cheetahregs.h>
#else /* sun4u */
#include <sys/niagararegs.h>
#endif /* sun4u */
#ifdef __cplusplus
extern "C" {
#endif
typedef enum cmd_cpu_type {
CPU_ULTRASPARC_III = 1,
typedef struct cmd_cpu_cases {
/*
* The UE cache. We actually have two UE caches - the current one and the old
* one. When it's time to flush the UE cache, we move the current UE cache to
* the old position and flush the E$. Then, we schedule the removal of the old
* UE cache. This allows a) xxUs triggered by the flush to match against the
* old cache, while b) still allowing new UEs to be added to the current UE
* cache. UE matches will always search in both caches (if present), but
* additions will only end up in the current cache. We go to all of this
* effort because the cost of a missed ereport (discarding due to a false match
* in the cache) is much less than that of a missed match. In the latter case,
* the CPU will be erroneously offlined.
*
* A special case is triggered if we see a UE with a not valid AFAR. Without
* the AFAR, we aren't able to properly match subsequent xxU's. As a result,
* we need to throw the cache into all-match mode, wherein all subsequent match
* attempts will succeed until the UE cache is flushed.
*/
typedef struct cmd_cpu_uec {
/*
* Certain types of xxC and xxU can trigger other types as side-effects. These
* secondary ereports need to be discarded, as treating them as legitimate
* ereports in their own right will cause erroneous diagnosis. As an example
* (see cmd_xxcu_trains for more), an L2$ UCC will usually trigger an L2$ WDC
* resulting from the trap handler's flushing of the L2$. If we treat both as
* legitimate, we'll end up adding two ereports to the SERD engine,
* significantly cutting the threshold for retiring the CPU.
*
* Our saving grace is the fact that the side-effect ereports will have the same
* ENA as the primary. As such, we can keep track of groups of ereports by ENA.
* These groups, which we'll call trains, can then be matched against a list of
* known trains. The list (an array of cmd_xxcu_train_t structures) has both a
* description of the composition of the train and an indication as to which of
* the received ereports is the primary.
*
* The cmd_xxcu_trw_t is used to gather the members of the train. When the
* first member comes in, we allocate a trw, recording the ENA of the ereport,
* as well as noting its class in trw_mask. We then reschedule the delivery of
* the ereport for some configurable time in the future, trusting that all
* members of the train will have arrived by that time. Subsequent ereports in
* the same train match the recorded ENA, and add themselves to the mask.
* When the first ereport is redelivered, trw_mask is used to determine whether
* or not a train has been seen. An exact match is required. If a match is
* made, the ereport indicated as the primary cause is used for diagnosis.
*/
typedef struct cmd_xxcu_trw {
extern void cmd_trw_restore(fmd_hdl_t *);
extern void cmd_trw_write(fmd_hdl_t *);
/*
* We don't have access to ereport nvlists when they are redelivered via timer.
* As such, we have to retrieve everything we might need for diagnosis when we
* first receive the ereport. The retrieved information is stored in the
* cmd_xr_t, which is persisted.
*/
/*
* xr_hdlr can't be persisted, so we use these in xr_hdlrid to indicate the
* handler to be used. xr_hdlr is then updated so it can be used directly.
*/
#define CMD_XR_HDLR_XXC 1
#define CMD_XR_HDLR_XXU 2
/*
* For sun4v, the size of xr_synd is expanded to 32 bits in order to
* accomodate the Niagara L2 syndrome (4x7 bits).
*/
struct cmd_xr {
#ifdef sun4u
#else /* sun4u */
#endif /* sun4u */
};
cmd_cpu_t *, cmd_errcl_t);
/*
* The master structure containing or referencing all of the state for a given
* CPU.
*/
/*
* We periodically flush the E$, thus allowing us to flush the UE cache (see
* above for a description of the UE cache). In particular, we flush it
* whenever we see a UE with a non-valid AFAR. To keep from overflushing the
* CPU, we cap the number of flushes that we'll do in response to UEs with
* cycle, and was determined arbitrarily.
*/
#define CPU_UEC_FLUSH_MAX 3
/*
* The CPU structure started life without a version number. Making things more
* complicated, the version number in the new struct occupies the space used for
* cpu_cpuid in the non-versioned struct. We therefore have to use somewhat
* unorthodox version numbers to distinguish between the two types of struct
* (pre- and post-versioning) -- version numbers that can't be mistaken for
* CPUIDs. Our version numbers, therefore, will be negative.
*
* For future expansion, the version member must always stay where it is. At
* some point in the future, when more structs get versions, the version member
* should move into the cmd_header_t.
*/
#define CMD_CPU_VERSION CMD_CPU_VERSION_2
#define CMD_CPU_F_DELETING 0x1
typedef struct cmd_cpu_0 {
} cmd_cpu_0_t;
typedef struct cmd_cpu_1 {
} cmd_cpu_1_t;
/* Portion of the bank structure which must be persisted */
typedef struct cmd_cpu_pers {
/* Persistent and dynamic CPU data */
struct cmd_cpu {
};
#define CMD_CPU_MAXSIZE \
sizeof (cmd_cpu_pers_t))
#define CMD_CPU_MINSIZE \
sizeof (cmd_cpu_pers_t))
/*
* L2$ and L3$ Data errors
*
* SERD name
* Type (if any) Fault
* ------ ----------- -------------------------------
* xxC l2cachedata fault.cpu.<cputype>.l2cachedata
* xxU - fault.cpu.<cputype>.l2cachedata
* L3_xxC l3cachedata fault.cpu.<cputype>.l3cachedata
* L3_xxU - fault.cpu.<cputype>.l3cachedata
*
* NOTE: For the purposes of the discussion below, xxC and xxU refer to both
* L2$ and L3$ data errors.
*
* These ereports will be dropped if (among other things) they are side-effects
* of UEs (xxUs only) or other xxCs or xxUs. Whenever UEs are detected, they
* are added to a per-CPU cache. xxUs are then compared to this cache. If a
* xxU's AFAR refers to an address which recently saw a UE, the xxU is dropped,
* as it was most likely caused by the UE. When multiple xxCs and xxUs are seen
* with the same ENA, all save one are generally side-effects. We track these
* groups (referred to as trains), matching them against a premade list. If one
* of the trains matches, we drop all but the primary, which is indicated in the
* list.
*
* The expected resolution of l2cachedata and l3cachedata faults is the
* disabling of the indicated CPU.
*/
const char *, cmd_errcl_t);
const char *, cmd_errcl_t);
/*
* L2$ and L3$ Tag errors
*
* SERD name
* Type (if any) Fault
* ------- ----------- -------------------------------
* TxCE l2cachetag fault.cpu.<cputype>.l2cachetag
* L3_THCE l3cachetag fault.cpu.<cputype>.l3cachetag
* LTC l2cachetag fault.cpu.<cputype>.l2cachetag
*
* We'll never see the uncorrectable Tag errors - they'll cause the machine to
* reset, and we'll be ne'er the wiser.
*
* The expected resolution of l2cachetag and l3cachetag faults is the disabling
* of the indicated CPU.
*/
const char *, cmd_errcl_t);
const char *, cmd_errcl_t);
/*
* L1$ errors
*
* SERD name
* Type (if any) Fault
* ------- --------- -------------------------------
* IPE icache fault.cpu.<cputype>.icache
* IxSPE icache fault.cpu.<cputype>.icache
* DPE dcache fault.cpu.<cputype>.dcache
* DxSPE dcache fault.cpu.<cputype>.dcache
* PDSPE pcache fault.cpu.<cputype>.pcache
*
* The I$, D$, and P$ are clean, and thus have no uncorrectable errors.
*
* The expected resolution of icache, dcache, and pcache faults is the disabling
* of the indicated CPU.
*/
const char *, cmd_errcl_t);
const char *, cmd_errcl_t);
const char *, cmd_errcl_t);
/*
* TLB errors
*
* SERD name
* Type (if any) Fault
* ------ --------- -------------------------------
* ITLBPE itlb fault.cpu.<cputype>.itlb
* DTLBPE dtlb fault.cpu.<cputype>.dtlb
*
* The expected resolution of itlb and dtlb faults is the disabling of the
* indicated CPU.
*/
const char *, cmd_errcl_t);
const char *, cmd_errcl_t);
extern void cmd_cpuerr_close(fmd_hdl_t *, void *);
/*
* FPU errors
*
* SERD name
* Type (if any) Fault
* ------ --------- -------------------------------
* FPU - fault.cpu.<cputype>.fpu
*
* The expected resolution of FPU faults is the disabling of the indicated CPU.
*/
const char *, cmd_errcl_t);
/*
* ireg errors
*
* SERD name
* Type (if any) Fault
* ------ --------- -------------------------------
* IRC ireg fault.cpu.<cputype>.ireg
* IRU - "
*
* The expected resolution of ireg faults is the disabling of the indicated CPU.
*/
const char *, cmd_errcl_t);
const char *, cmd_errcl_t);
/*
* freg errors
*
* SERD name
* Type (if any) Fault
* ------ --------- -------------------------------
* FRC freg fault.cpu.ultraSPARC-T1.frc
* FRU - " .fru
*
* The expected resolution of freg faults is the repair of the indicated CPU.
*/
const char *, cmd_errcl_t);
const char *, cmd_errcl_t);
/*
* MAU errors
*
* SERD name
* Type (if any) Fault
* ------ --------- -------------------------------
* MAU mau fault.cpu.<cputype>.mau
*
* The expected resolution of mau faults is the repair of the indicated CPU.
*/
const char *, cmd_errcl_t);
/*
* L2CTL errors
*
* SERD name
* Type (if any) Fault
* ------ --------- -------------------------------
* L2CTL - fault.cpu.<cputype>.l2ctl
*
* The expected resolution of l2ctl faults is the repair of the indicated CPU.
*/
const char *, cmd_errcl_t);
/*
* CPUs are described by FMRIs. This routine will retrieve the CPU state
* structure (creating a new one if necessary) described by the detector
* FMRI in the passed ereport.
*/
const char *);
extern void cmd_cpu_validate(fmd_hdl_t *);
extern void cmd_cpu_gc(fmd_hdl_t *);
typedef enum {
} cpu_family_t;
extern cpu_family_t cmd_cpu_check_support(void);
#ifdef sun4u
extern int cmd_cpu_synd_check(uint16_t);
#else /* sun4u */
extern int cmd_cpu_synd_check(uint32_t);
#endif /* sun4u */
#ifdef __cplusplus
}
#endif
#endif /* _CMD_CPU_H */