fx_fabric.c revision 4df55fde49134f9735f84011f23a767c75e393c7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include <stddef.h>
#include <strings.h>
#include "fabric-xlate.h"
static fab_err_tbl_t *fab_master_err_tbl;
/*
* Translation tables for converting "fabric" error bits into "pci" ereports.
* <Ereport Class Name>, <Error Bit Mask>, <Preparation Function>
*/
/* MACRO for table entries with no TGT ereports */
/* Translate Fabric ereports to ereport.io.pci.* */
};
/* Translate Fabric ereports to ereport.io.pci.sec-* */
static fab_erpt_tbl_t fab_pci_bdg_erpt_tbl[] = {
#ifdef sparc
#endif
};
/* Translate Fabric ereports to ereport.io.pci.dto */
static fab_erpt_tbl_t fab_pci_bdg_ctl_erpt_tbl[] = {
};
/* Translate Fabric ereports to ereport.io.pciex.* */
static fab_erpt_tbl_t fab_pcie_ce_erpt_tbl[] = {
};
/*
* Translate Fabric ereports to ereport.io.pciex.*
* The Target Ereports for this section is only used on leaf devices, with the
* exception of TO
*/
static fab_erpt_tbl_t fab_pcie_ue_erpt_tbl[] = {
#ifdef sparc
#endif
};
/* Translate Fabric ereports to ereport.io.pciex.* */
static fab_erpt_tbl_t fab_pcie_sue_erpt_tbl[] = {
#ifdef sparc
#endif
};
/* Translate Fabric ereports to ereport.io.pcix.* */
static fab_erpt_tbl_t fab_pcix_erpt_tbl[] = {
};
/* Translate Fabric ereports to ereport.io.pcix.sec-* */
static fab_erpt_tbl_t fab_pcix_bdg_sec_erpt_tbl[] = {
};
/* Translate Fabric ereports to ereport.io.pciex.* */
static fab_erpt_tbl_t fab_pcie_nadv_erpt_tbl[] = {
#ifdef sparc
#endif
};
/* Translate Fabric ereports to ereport.io.pciex.* */
static fab_erpt_tbl_t fab_pcie_rc_erpt_tbl[] = {
};
/*
* Translate Fabric ereports to pseudo ereport.io.pciex.* RC Fabric Messages.
* If the RP is not a PCIe compliant RP or does not support AER, rely on the
* leaf fabric ereport to help create a xxx_MSG ereport coming from the RC.
*/
static fab_erpt_tbl_t fab_pcie_fake_rc_erpt_tbl[] = {
};
/* ARGSUSED */
void
{
/* Generic PCI device information */
/* Misc ereport information */
/* PCI registers */
/* PCI bridge registers */
/* PCIx registers */
/* PCIx ECC Registers */
/* PCIx ECC Bridge Registers */
/* PCIx Bridge */
/* PCIe registers */
/* PCIe AER registers */
/* PCIe BDG AER registers */
/* PCIe RP registers */
/* PCIe RP AER registers */
/*
* If the system has a PCIe complaint RP with AER, turn off translating
* fake RP ereports.
*/
if (fab_xlate_fake_rp &&
}
static int
{
/* Generate an ereport for this error bit. */
return (err);
}
static int
{
/* Generate an ereport for this error bit. */
return (err);
}
static int
{
/* Generate an ereport for this error bit. */
return (err);
}
static int
{
/* Generate an ereport for this error bit. */
return (err);
}
static int
{
/* Generate an ereport for this error bit. */
} else {
}
}
return (err);
}
static int
{
/* Generate an ereport for this error bit. */
} else {
}
}
return (err);
}
static int
{
int err = 0;
/* Only send if this is not a bridge */
return (1);
/* Generate an ereport for this error bit. */
return (err);
}
static void
{
switch (ecc_phase) {
case PCI_PCIX_ECC_PHASE_NOERR:
break;
case PCI_PCIX_ECC_PHASE_FADDR:
case PCI_PCIX_ECC_PHASE_SADDR:
"%s.%s", PCIX_ERROR_SUBCLASS,
break;
case PCI_PCIX_ECC_PHASE_ATTR:
"%s.%s", PCIX_ERROR_SUBCLASS,
break;
"%s.%s", PCIX_ERROR_SUBCLASS,
break;
}
if (ecc_phase) {
goto done;
data->pcix_command);
}
"%s.%s", PCIX_ERROR_SUBCLASS,
goto done;
data->pcix_command);
}
return;
done:
}
static int
{
/* Generate an ereport for this error bit. */
return (err);
}
static int
{
/* Generate an ereport for this error bit. */
return (err);
}
static void
{
switch (ecc_phase) {
case PCI_PCIX_ECC_PHASE_NOERR:
break;
case PCI_PCIX_ECC_PHASE_FADDR:
case PCI_PCIX_ECC_PHASE_SADDR:
break;
case PCI_PCIX_ECC_PHASE_ATTR:
break;
break;
}
if (ecc_phase) {
goto done;
}
goto done;
}
return;
done:
}
static int
{
int err = 0;
/* Don't send this for PCI device, Root Ports, or PCIe with AER */
return (1);
/* Generate an ereport for this error bit. */
return (err);
}
static int
{
int err = 0;
return (-1);
/* Only send a FE Msg if the 1st UE error is FE */
if (!(status & PCIE_AER_RE_STS_FIRST_UC_FATAL))
return (-1);
else
isFE = 1;
/* Only send a NFE Msg is the 1st UE error is NFE */
return (-1);
else
isNFE = 1;
/* Generate an ereport for this error bit. */
}
}
return (err);
}
static int
{
uint32_t rc_err_sts = 0;
int err = 0;
/*
* Don't send this for PCI device or Root Ports. Only send it on
* systems with non-compliant RPs.
*/
return (-1);
/* Generate an ereport for this error bit. */
/* Send PCIe RC Ereports */
}
}
}
}
if (!(rc_err_sts & PCIE_AER_RE_STS_MUL_FE_NFE_RCVD)) {
}
return (err);
}
void
{
/* Go through the error logs and send the relavant reports */
}
/* Send PCI-X ECC Ereports */
}
void
{
fab_data_t data = {0};
}
void
{
/* Setup the master error table */
sizeof (fab_err_tbl_t));
}