fabric-xlate.h revision 4df55fde49134f9735f84011f23a767c75e393c7
1N/A/*
1N/A * CDDL HEADER START
1N/A *
1N/A * The contents of this file are subject to the terms of the
1N/A * Common Development and Distribution License (the "License").
1N/A * You may not use this file except in compliance with the License.
1N/A *
1N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
1N/A * or http://www.opensolaris.org/os/licensing.
1N/A * See the License for the specific language governing permissions
1N/A * and limitations under the License.
1N/A *
1N/A * When distributing Covered Code, include this CDDL HEADER in each
1N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1N/A * If applicable, add the following below this CDDL HEADER, with the
1N/A * fields enclosed by brackets "[]" replaced with your own identifying
1N/A * information: Portions Copyright [yyyy] [name of copyright owner]
1N/A *
1N/A * CDDL HEADER END
1N/A */
1N/A/*
1N/A * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
1N/A * Use is subject to license terms.
1N/A */
1N/A
1N/A#ifndef _FABRIC_XLATE_H
1N/A#define _FABRIC_XLATE_H
1N/A
1N/A#include <fm/fmd_api.h>
1N/A#include <sys/fm/protocol.h>
1N/A#include <sys/nvpair.h>
1N/A#include <sys/types.h>
1N/A#include <sys/pcie.h>
1N/A#include <sys/fm/io/pci.h>
1N/A
1N/A#ifdef __cplusplus
1N/Aextern "C" {
1N/A#endif
1N/A
1N/A#define STRCMP(s1, s2) (strcmp((const char *)s1, (const char *)s2) == 0)
1N/A/*
1N/A * These values are used for the xxx_tgt_trans value in fab_data_t. They are
1N/A * originally set in pcie_fault.c and originally defined in pcie_impl.h.
1N/A */
1N/A#define PF_ADDR_DMA (1 << 0)
1N/A#define PF_ADDR_PIO (1 << 1)
1N/A#define PF_ADDR_CFG (1 << 2)
1N/A
1N/Aextern fmd_xprt_t *fab_fmd_xprt; /* FMD transport layer handle */
1N/Aextern char fab_buf[];
1N/A
1N/A/* PCI-E config space data for error handling and fabric ereports */
1N/Atypedef struct fab_data {
1N/A /* Original ereport NVL */
1N/A nvlist_t *nvl;
1N/A
1N/A /* Device Information */
1N/A uint16_t bdf;
1N/A uint16_t device_id;
1N/A uint16_t vendor_id;
1N/A uint8_t rev_id;
1N/A uint16_t dev_type;
1N/A uint16_t pcie_off;
1N/A uint16_t pcix_off;
1N/A uint16_t aer_off;
1N/A uint16_t ecc_ver;
1N/A
1N/A /* Ereport Information */
1N/A uint32_t remainder;
1N/A uint32_t severity;
1N/A
1N/A /* Error Registers */
1N/A uint16_t pci_err_status; /* pci status register */
1N/A uint16_t pci_cfg_comm; /* pci command register */
1N/A
1N/A uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */
1N/A uint16_t pci_bdg_ctrl; /* PCI bridge control reg */
1N/A
1N/A uint16_t pcix_command; /* pcix command register */
1N/A uint32_t pcix_status; /* pcix status register */
1N/A
1N/A uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */
1N/A uint32_t pcix_bdg_stat; /* pcix bridge status reg */
1N/A
1N/A uint16_t pcix_ecc_control_0; /* pcix ecc control status reg */
1N/A uint16_t pcix_ecc_status_0; /* pcix ecc control status reg */
1N/A uint32_t pcix_ecc_fst_addr_0; /* pcix ecc first address reg */
1N/A uint32_t pcix_ecc_sec_addr_0; /* pcix ecc second address reg */
1N/A uint32_t pcix_ecc_attr_0; /* pcix ecc attributes reg */
1N/A uint16_t pcix_ecc_control_1; /* pcix ecc control status reg */
1N/A uint16_t pcix_ecc_status_1; /* pcix ecc control status reg */
1N/A uint32_t pcix_ecc_fst_addr_1; /* pcix ecc first address reg */
1N/A uint32_t pcix_ecc_sec_addr_1; /* pcix ecc second address reg */
1N/A uint32_t pcix_ecc_attr_1; /* pcix ecc attributes reg */
1N/A
1N/A uint16_t pcie_err_status; /* pcie device status register */
1N/A uint16_t pcie_err_ctl; /* pcie error control register */
1N/A uint32_t pcie_dev_cap; /* pcie device capabilities register */
1N/A
1N/A uint32_t pcie_adv_ctl; /* pcie advanced control reg */
1N/A uint32_t pcie_ue_status; /* pcie ue error status reg */
1N/A uint32_t pcie_ue_mask; /* pcie ue error mask reg */
1N/A uint32_t pcie_ue_sev; /* pcie ue error severity reg */
1N/A uint32_t pcie_ue_hdr[4]; /* pcie ue header log */
1N/A uint32_t pcie_ce_status; /* pcie ce error status reg */
1N/A uint32_t pcie_ce_mask; /* pcie ce error mask reg */
1N/A uint32_t pcie_ue_tgt_trans; /* Fault trans type from AER Logs */
1N/A uint64_t pcie_ue_tgt_addr; /* Fault addr from AER Logs */
1N/A pcie_req_id_t pcie_ue_tgt_bdf; /* Fault bdf from SAER Logs */
1N/A boolean_t pcie_ue_no_tgt_erpt; /* Don't send target ereports */
1N/A
1N/A uint32_t pcie_sue_ctl; /* pcie bridge secondary ue control */
1N/A uint32_t pcie_sue_status; /* pcie bridge secondary ue status */
1N/A uint32_t pcie_sue_mask; /* pcie bridge secondary ue mask */
1N/A uint32_t pcie_sue_sev; /* pcie bridge secondary ue severity */
1N/A uint32_t pcie_sue_hdr[4]; /* pcie bridge secondary ue hdr log */
1N/A uint32_t pcie_sue_tgt_trans; /* Fault trans type from AER Logs */
1N/A uint64_t pcie_sue_tgt_addr; /* Fault addr from AER Logs */
1N/A pcie_req_id_t pcie_sue_tgt_bdf; /* Fault bdf from SAER Logs */
1N/A
1N/A uint32_t pcie_rp_status; /* root complex status register */
1N/A uint16_t pcie_rp_ctl; /* root complex control register */
1N/A uint32_t pcie_rp_err_status; /* pcie root complex error status reg */
1N/A uint32_t pcie_rp_err_cmd; /* pcie root complex error cmd reg */
1N/A uint16_t pcie_rp_ce_src_id; /* pcie root complex ce sourpe id */
1N/A uint16_t pcie_rp_ue_src_id; /* pcie root complex ue sourpe id */
1N/A} fab_data_t;
1N/A
1N/Atypedef struct fab_erpt_tbl {
1N/A const char *err_class; /* Final Ereport Class */
1N/A uint32_t reg_bit; /* Error Bit Mask */
1N/A /* Pointer to function that prepares the ereport body */
1N/A const char *tgt_class; /* Target Ereport Class */
1N/A} fab_erpt_tbl_t;
1N/A
1N/Atypedef struct fab_err_tbl {
1N/A fab_erpt_tbl_t *erpt_tbl; /* ereport table */
1N/A uint32_t reg_offset; /* sts reg for ereport table offset */
1N/A uint32_t reg_size; /* size of the status register */
1N/A /* Pointer to function that prepares the ereport body */
1N/A int (*fab_prep)(fmd_hdl_t *, fab_data_t *, nvlist_t *,
1N/A fab_erpt_tbl_t *);
1N/A} fab_err_tbl_t;
1N/A
1N/Aextern void fab_setup_master_table();
1N/A
1N/A/* Main functions for converting "fabric" ereports */
1N/Aextern void fab_xlate_pcie_erpts(fmd_hdl_t *, fab_data_t *);
1N/Aextern void fab_xlate_fabric_erpts(fmd_hdl_t *, nvlist_t *, const char *);
1N/Aextern void fab_xlate_fire_erpts(fmd_hdl_t *, nvlist_t *, const char *);
1N/Aextern void fab_xlate_epkt_erpts(fmd_hdl_t *, nvlist_t *, const char *);
1N/A
1N/A/* Common functions for sending translated ereports */
1N/Aextern int fab_prep_basic_erpt(fmd_hdl_t *, nvlist_t *, nvlist_t *, boolean_t);
1N/Aextern void fab_send_tgt_erpt(fmd_hdl_t *, fab_data_t *, const char *,
1N/A boolean_t);
1N/Aextern void fab_send_erpt(fmd_hdl_t *hdl, fab_data_t *data, fab_err_tbl_t *tbl);
1N/A
1N/A/* Misc Functions */
1N/Aextern void fab_pr(fmd_hdl_t *, fmd_event_t *, nvlist_t *);
1N/Aextern boolean_t fab_get_rcpath(fmd_hdl_t *hdl, nvlist_t *nvl, char *rcpath);
1N/Aextern char *fab_find_rppath_by_df(fmd_hdl_t *, nvlist_t *, uint8_t);
1N/Aextern char *fab_find_rppath_by_devbdf(fmd_hdl_t *, nvlist_t *, pcie_req_id_t);
1N/Aextern char *fab_find_addr(fmd_hdl_t *hdl, nvlist_t *nvl, uint64_t addr);
1N/Aextern char *fab_find_bdf(fmd_hdl_t *hdl, nvlist_t *nvl, pcie_req_id_t bdf);
1N/Aextern boolean_t fab_hc2dev(fmd_hdl_t *, const char *, char **);
1N/Aextern boolean_t fab_hc2dev_nvl(fmd_hdl_t *, nvlist_t *, char **);
1N/A
1N/A#ifdef __cplusplus
1N/A}
1N/A#endif
1N/A
1N/A#endif /* _FABRIC_XLATE_H */
1N/A