gcpu.esc revision e4b86885570d77af552e9cf94f142f4d744fb8c8
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* eversholt rules for generic x86 MCA
*
* Most propogations are generated by preprocessor macros. The event
* declarations are deliberately not part of the propogation macros
* so that we know we have full coverage - propogations defined without
* events, or events not used in propogations, will produce compiler
* whinges.
*/
/*
* Ereports for Simple error codes.
*/
/*
* Propogations for all but "external" and "unknown" simple errors.
* If the error is uncorrected we produce a fault immediately by incrementing
* by N+1, otherwise we declare a fault when the SERD engine trips.
*/
/*
* Ereports for Compound error codes. These are in pairs "foo" and "foo_uc"
* for the corrected and uncorrected version of each error type. All are
*/
{ within(1s) }; \
{ within(1s) }
/*
* Ereports for Compound error codes - generic memory hierarchy errors
*/
/*
* Ereports for Compound error codes - TLB errors
*/
/*
* Ereports for Compound error codes - memory hierarchy errors
*/
/*
* Ereports for Compound error codes - bus and interconnect errors
*/
/*
* Compound error propogations
*
* We resist the temptation propogate, for example, a single dcache fault
* to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache).
* Instead we will diagnose a distinct fault for each possible cache level,
* whether or not current chips have dcaches at all levels.
*
* Corrected errors are SERDed and produce a fault when the engine fires;
* the same fault is diagnosed immediately for a corresponding uncorrected
* error by incrementing the serd engine by n + 1.
*/
\
\
/*
* Discards - not enough info to diagnose.
*/