7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * CDDL HEADER START
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7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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5667185bc023b9742cb2480659d7673fa9ac8050Srihari Venkatesan * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Use is subject to license terms.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Eversholt rules for the AMD Opteron CPU/Memory
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * we diagnose for page faults, to record the physical address of the faulting
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define SET_ADDR (setpayloadprop("asru-physaddr", payloadprop("IA32_MCi_ADDR")))
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * RESOURCE_EXISTS is true if a member with name "resource" exists in the
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * payload - regardless of type (e.g., nvlist or nvlist array) or value.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#define RESOURCE_EXISTS (payloadprop_defined("resource"))
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * CONTAINS_RANK is true if the "resource" nvlist array (as used in memory
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * ereports) exists and one if its members matches the path for the
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * rank node. Our memory propogation are of the form
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye * "prop foo@chip/memory-controller/dimm/rank -> blah@chip/core/strand"
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * since cpus detect memory errors; in eversholt such a propogation, where
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * the lhs path and rhs path do not match, expands to the cross-product of
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * all dimms, ranks and cpus on the same chip (since chip appears in the
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * path on both sides). We use CONTAINS_RANK to constrain the propogation
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * such that it only happens if the payload resource matches the rank.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm#define CONTAINS_RANK (payloadprop_contains("resource", \
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * The following will tell us whether a syndrome that is known to be
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * correctable (from a mem_ce ereport) is single-bit or multi-bit. For a
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * correctable ChipKill syndrome the number of bits set in the lowest
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * nibble indicates how many bits were in error.
5667185bc023b9742cb2480659d7673fa9ac8050Srihari Venkatesan (payloadprop("syndrome-type") == "C4" && \
5667185bc023b9742cb2480659d7673fa9ac8050Srihari Venkatesan (payloadprop("syndrome-type") == "C4" && \
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * #DIMM_SCU#
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * A single bit fault in a memory rank can cause:
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * - mem_ce : reported by nb
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * - inf_sys_ecc1: reported by ic or dc; inf_sys_ecc1 errors detected at the
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * ic do not record a syndrome; these errors will not be triggered in
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * ChipKill ECC mode (the NB corrects all ECC errors in that mode)
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * - s_ecc1: reported by bu; this error will not be triggered in ChipKill
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * ECC mode (the NB corrects all ECC in that mode)
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Single-bit errors are fed into a per-rank SERD engine; if a SERD engine
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * trips we diagnose a fault.memory.page so that the response agent can
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * retire the page that caused the trip. If the total number of pages
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * faulted in this way on a single rank exceeds a threshold we will
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * diagnose a fault.memory.dimm_sb against the containing dimm.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Multibit ChipKill-correctable errors are treated identically to
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * single-bit errors, but via separate serd engines to allow distinct
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * parameters if desired.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Uncorrectable errors produce an immediate page fault and corresponding
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * fault.memory.dimm_ue.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Page faults are essentially internal - action is only required when
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * they are accompanied by a dimm fault. As such we include message=0
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * on page faults.
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.inf_sys_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.inf_sys_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.s_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.mem_ce@chip/core/strand{within(5s)};
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * Single-bit correctable errors feed into per-rank
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * SERD engines which diagnose fault.memory.page_sb if they trip.
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * Multi-bit correctable (via ChipKill) errors feed
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * into additional per-rank SERD engines which diagnose fault.memory.page_ck
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * if they trip.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The number of fault.memory.page and fault.memory.page_ck diagnosed is
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * counted in stat engines for each type. These are used in deciding
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * whether to declare a dimm faulty after repeated page faults.
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhengine serd.memory.page_sb@chip/memory-controller/dimm/rank,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhengine serd.memory.page_ck@chip/memory-controller/dimm/rank,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhengine serd.memory.dimm_sb@chip/memory-controller/dimm/rank,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhengine serd.memory.dimm_ck@chip/memory-controller/dimm/rank,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.memory.page_sb@chip/memory-controller/dimm/rank, message=0,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh count=stat.sbpgflt@chip/memory-controller/dimm/rank, response=0,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh engine=serd.memory.page_sb@chip/memory-controller/dimm/rank;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.memory.page_ck@chip/memory-controller/dimm/rank, message=0,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh count=stat.ckpgflt@chip/memory-controller/dimm/rank, response=0,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh engine=serd.memory.page_ck@chip/memory-controller/dimm/rank;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.memory.dimm_sb@chip/memory-controller/dimm/rank,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh engine=serd.memory.dimm_sb@chip/memory-controller/dimm/rank;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.memory.dimm_ck@chip/memory-controller/dimm/rank,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh engine=serd.memory.dimm_ck@chip/memory-controller/dimm/rank;
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The fraction of pages on a single rank that must be diagnosed as faulty
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * with single correctable unit faults before we will fault the rank.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Once we have faulted the rank we will continue to diagnose any further page
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * faults on the rank up to some maximum multiple of the threshold at which
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * we faulted the dimm. This allows us to potentially contain some fairly
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * far-reaching but still limited-extent fault (such as a partial column
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * failure) without getting carried away and allowing a single faulty rank to
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * use up the entire system-imposed page retirenment limit (which, once
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * reached, causes retirement request to have no effect other than to fill
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * the fault manager cache and logs).
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * This fraction is specified in basis points, where 100 basis points are
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * equivalent to 1 percent. It is applied on a per-rank basis.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The system imposes an absolute maximum on the number of pages it will
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * retire; the current value is 10 basis points, or 0.1% of 'physmem'. Note
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * that 'physmem' is reduced from installed memory pages by an amount
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * reflecting permanent kernel memory allocations. This system page retire
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * limit bounds the maximum real response to page faults across all ranks
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * that fault manager response agents can effect, but it should not be confused
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * with any diagnosis threshold (i.e., the number of faulty pages we are
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * prepared to tolerate from a single rank before faulting the rank is
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * distinct from the total number of pages we are prepared to retire from use
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * in response to that and other faults). It is, however, desirable to
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * arrange that the maximum number of pages we are prepared to fault from
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * any one rank is less than the system-wide quota.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm#define PAGE_RETIRE_LIMIT_BPS 5 /* or 0.05%; ~ 131 pages/GB %/
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * A macro to manipulate the above fraction. Given a size in bytes convert
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * this to pages (4K pagesize) and calculate the number of those pages
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * indicated by PAGE_RETIRE_LIMIT_BPS basis points.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm ((((totalbytes) / 4096 ) * PAGE_RETIRE_LIMIT_BPS) / 10000)
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The single-correctable-unit threshold at which number of faulted pages
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * on a rank we we fault the rank. We insist that this be at least 128 and
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * never more than 512.
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh _BPS_PGCNT(confprop(chip/memory-controller/dimm/rank, "size"))))
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The maximum number of single-correctable-unit page faults we will diagnose
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * on a single rank (must be greater than RANK_THRESH). We set
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * this at twice the rank fault threshold.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm#define SB_PGFLTS (count(stat.sbpgflt@chip/memory-controller/dimm/rank))
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm#define CK_PGFLTS (count(stat.ckpgflt@chip/memory-controller/dimm/rank))
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * "Single-correctable-unit" DIMM faults are diagnosed when the total number of
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * page faults (diagnosed from repeated single-bit or multibit-chipkills)
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * from any one rank on that DIMM reaches a threshold. A "correctable unit"
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * is a single bit in normal 64/8 ECC mode, or a single symbol in ChipKill
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * 128/16 mode (i.e., nibble-aligned nibble for the code used on Opteron).
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * We do not stop diagnosing further single-bit page faults once we have
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * declared a single-bit DIMM fault - we continue diagnosing them and
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * response agents can continue to retire those pages up to the system-imposed
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * retirement limit.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Two distinct fault types may be diagnosed - fault.memory.dimm_sb and
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * fault.memory.dimm_ck. Which one is diagnosed depends on whether we
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * have reached the threshold for a majority of single-bit page faults or
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * multibit page faults.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Implementation: we maintain parallel SERD engines to the page_sb and
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * page_ck engines, which trip in unison. On trip it generates a distinct
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * ereport which we diagnose to a fault if the threshold has been reached.
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhprop fault.memory.page_sb@chip/memory-controller/dimm/rank
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh SB_PGFLTS + CK_PGFLTS < RANK_PGFLT_MAX && SET_ADDR && SET_OFFSET } (1)->
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.dc.inf_sys_ecc1@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.bu.s_ecc1@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.nb.mem_ce@chip/core<>/strand<>;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhprop fault.memory.page_ck@chip/memory-controller/dimm/rank
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh SB_PGFLTS + CK_PGFLTS < RANK_PGFLT_MAX && SET_ADDR && SET_OFFSET } (1)->
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.dc.inf_sys_ecc1@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.bu.s_ecc1@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.nb.mem_ce@chip/core<>/strand<>;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhprop fault.memory.dimm_sb@chip/memory-controller/dimm/rank
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh { CONTAINS_RANK && SB_PGFLTS + CK_PGFLTS > RANK_THRESH &&
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.dc.inf_sys_ecc1@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.bu.s_ecc1@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.nb.mem_ce@chip/core<>/strand<>;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhprop fault.memory.dimm_ck@chip/memory-controller/dimm/rank
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh { CONTAINS_RANK && SB_PGFLTS + CK_PGFLTS > RANK_THRESH &&
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.nb.mem_ce@chip/core<>/strand<>;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * If the address is not valid then no resource member will be included
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * in a nb.mem_ce or nb.mem_ue ereport. These cases should be rare.
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * We will also discard all inf_sys_ecc1 events detected at the ic since they
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * have no syndrome and therefore no resource information.
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * We will discard such ereports. An alternative may be to SERD them
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * on a per MC basis and trip if we see too many such events.
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.ic.inf_sys_ecc1@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.inf_sys_ecc1@chip/core/strand,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #DIMM_UE#
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * #PAGE_UE#
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * An uncorrectable multi-bit fault in a memory dimm can cause:
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * - mem_ue : reported by nb for an access from a remote cpu
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * - inf_sys_eccm : reported by ic or dc; the ic does not report a syndrome
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * - s_eccm : reported by bu
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Since on production systems we force HT Sync Flood on uncorrectable
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * memory errors (if not already set as such by the BIOS, as it should be)
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * we won't actually receive these ereports since the system will be reset.
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.inf_sys_eccm@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.inf_sys_eccm@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.s_eccm@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.mem_ue@chip/core/strand{within(5s)};
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.memory.dimm_ue@chip/memory-controller/dimm/rank;
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.memory.page_ue@chip/memory-controller/dimm/rank, message=0,
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhprop fault.memory.dimm_ue@chip/memory-controller/dimm/rank
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.ic.inf_sys_eccm@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.dc.inf_sys_eccm@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.bu.s_eccm@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.nb.mem_ue@chip/core<>/strand<>;
8a40a695ee676a322b094e9afe5375567bfb51e3gavinmprop fault.memory.page_ue@chip/memory-controller/dimm/rank
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.ic.inf_sys_eccm@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.dc.inf_sys_eccm@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.bu.s_eccm@chip/core<>/strand<>,
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hanson ereport.cpu.amd.nb.mem_ue@chip/core<>/strand<>;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.ic.inf_sys_eccm@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.inf_sys_eccm@chip/core/strand,
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm/* #CSTESTFAIL#
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * If the BIOS fails a chip-select during POST, or perhaps after a
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * sync flood from an uncorrectable error, then on revision F and G it
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * should mark that chip-select as TestFail in the CS Base register.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * When the memory-controller driver discovers all the MC configuration
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * it notes such failed chip-selects and creates topology nodes for the
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * chip-select and associated dimms and ranks, and produces an ereport for each
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * failed chip-select with detector set to the memory-controller node
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * and resource indicating the failed chip-select.
b5016cbb2b36f686c5935adc6174dbb3b959c214stephhevent ereport.cpu.amd.mc.cs_testfail@chip/memory-controller{within(5s)};
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.memory.dimm_testfail@chip/memory-controller/dimm/rank;
8a40a695ee676a322b094e9afe5375567bfb51e3gavinmevent error.memory.cs_testfail@chip/memory-controller/chip-select;
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm#define CONTAINS_CS (payloadprop_contains("resource", \
b5016cbb2b36f686c5935adc6174dbb3b959c214stephhprop error.memory.cs_testfail@chip/memory-controller/chip-select (1)->
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm ereport.cpu.amd.mc.cs_testfail@chip/memory-controller
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh (confprop_defined(chip/memory-controller/chip-select, s) && \
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh confprop(chip/memory-controller/dimm/rank, "csname"))
8cffa125fa3761e4ea4b99a01cb1207e1d90e740Stephen Hansonprop fault.memory.dimm_testfail@chip/memory-controller/dimm/rank (0)->
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm error.memory.cs_testfail@chip/memory-controller/chip-select
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm { CSMATCH("dimm1-csname") || CSMATCH("dimm2-csname")};
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm/* #ADDRPAR#
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * DRAM Command/Address Parity Errors.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * - dramaddr_par : reported by the nb; the NB status register includes
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * a bit indicating which dram controller channel (A or B) experienced
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * the error.
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.dramaddr_par@chip/core/strand{within(5s)};
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephhevent fault.cpu.amd.dramchannel@chip/memory-controller/dram-channel, response=0;
8a40a695ee676a322b094e9afe5375567bfb51e3gavinmprop fault.cpu.amd.dramchannel@chip/memory-controller/dram-channel[y] (0)->
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.nb.dramaddr_par@chip/core/strand {
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh ((payloadprop("IA32_MCi_STATUS") >> 32 & 0x200) ? 1 : 0) == y };
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #L2D_SINGLE#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A single bit data array fault in an l2 cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - inf_l2_ecc1 : reported by ic on this cpu
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - inf_l2_ecc1 : reported by dc on this cpu
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2d_ecc1 : reported by bu on copyback or on snoop from another cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.inf_l2_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.inf_l2_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.l2d_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.l2cachedata@chip/core/strand, engine=serd.cpu.amd.l2d_sb@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.l2cachedata@chip/core/strand (0)->
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.ic.inf_l2_ecc1@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.inf_l2_ecc1@chip/core/strand,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #L2D_MULTI#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A multi-bit data array fault in an l2 cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - inf_l2_eccm : reported by ic on this cpu
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - inf_l2_eccm : reported by dc on this cpu
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2d_eccm : reported by bu on copyback or on snoop from another cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.inf_l2_eccm@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.inf_l2_eccm@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.l2d_eccm@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.l2cachedata@chip/core/strand
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.ic.inf_l2_eccm@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.inf_l2_eccm@chip/core/strand,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #L2T_SINGLE#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A single bit tag array fault in an l2 cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2t_ecc1 : reported by bu on this cpu when detected during snoop
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2t_par : reported by bu on this cpu when detected other than during snoop
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.l2t_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.l2t_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.l2cachetag@chip/core/strand, engine=serd.cpu.amd.l2t_sb@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.l2cachetag@chip/core/strand (0)->
c7d6cfd6e2ae5d7536ef67f65110733890f370a4Stephen Hanson ereport.cpu.amd.bu.l2t_ecc1@chip/core/strand;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #L2T_MULTI#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A multi-bit tag array fault in an l2 cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2t_eccm : reported by bu on this cpu when detected during snoop
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2t_par : reported by bu on this cpu when detected other than during snoop
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.l2t_eccm@chip/core/strand{within(5s)};
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #ICD_PAR#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A data array parity fault in an I cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - data_par : reported by ic on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.data_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeengine serd.cpu.amd.icachedata@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.icachedata@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye engine=serd.cpu.amd.icachedata@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.icachedata@chip/core/strand (0)->
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #ICT_PAR#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A tag array parity fault in an I cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - tag_par : reported by ic on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.tag_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeengine serd.cpu.amd.icachetag@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.icachetag@chip/core/strand, engine=serd.cpu.amd.icachetag@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.icachetag@chip/core/strand (0)->
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #ICT_SNOOP#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A snoop tag array parity fault in an I cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - stag_par : reported by ic on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.stag_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.icachestag@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.icachestag@chip/core/strand (1)->
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #ICTLB_1#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * An l1tlb parity fault in an I cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l1tlb_par : reported by ic on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.l1tlb_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.l1itlb@chip/core/strand, engine=serd.cpu.amd.l1itlb@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.l1itlb@chip/core/strand (0)->
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.ic.l1tlb_par@chip/core/strand;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #ICTLB_2#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * An l2tlb parity fault in an I cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2tlb_par : reported by ic on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.l2tlb_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.l2itlb@chip/core/strand, engine=serd.cpu.amd.l2itlb@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.l2itlb@chip/core/strand (0)->
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.ic.l2tlb_par@chip/core/strand;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #DCD_SINGLE#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A single bit data array fault in an D cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - data_ecc1 : reported by dc on this cpu by scrubber
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - data_ecc1_uc : reported by dc on this cpu other than by scrubber
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * Make data_ecc1_uc fault immediately as it may have caused a panic, so
b7d3956b92a285d8dac2c7f5f7e28d2ef5347ef8stephh * it is handled by the multi-bit case in the following section.
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.data_ecc1@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.data_ecc1_uc@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.dcachedata@chip/core/strand, engine=serd.cpu.amd.dc_sb@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.dcachedata@chip/core/strand (0)->
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.data_ecc1@chip/core/strand;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #DCD_MULTI#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A multi-bit data array fault in an D cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - data_eccm : reported by dc on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.data_eccm@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.data_eccm@chip/core/strand,
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.data_ecc1_uc@chip/core/strand;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #DCT_PAR#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A tag array parity fault in an D cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - tag_par : reported by dc on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.tag_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.dcachetag@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.dcachetag@chip/core/strand (1)->
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #DCT_SNOOP#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * A snoop tag array parity fault in an D cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - stag_par : reported by dc on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.stag_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent fault.cpu.amd.dcachestag@chip/core/strand;
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.dcachestag@chip/core/strand (1)->
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #DCTLB_1#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * An l1tlb parity fault in an D cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l1tlb_par : reported by dc on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.l1tlb_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.l1dtlb@chip/core/strand (1)->
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.l1tlb_par@chip/core/strand;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/* #DCTLB_2#
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * An l2tlb parity fault in an D cache can cause:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - l2tlb_par : reported by dc on this cpu
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.dc.l2tlb_par@chip/core/strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeprop fault.cpu.amd.l2dtlb@chip/core/strand (1)->
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Ye ereport.cpu.amd.dc.l2tlb_par@chip/core/strand;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Ereports that should not normally happen and which we will discard
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * without diagnosis if they do. These fall into a few categories:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - the corresponding detector is not enabled, typically because
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * detection/handling of the event is taking place elsewhere
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * (nb.ma, nb.ta, ls.rde, ic.rdde, bu.s_rde, nb.gart_walk)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - the event is associated with a sync flood so even if the detector is
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * enabled we will never handle the event and generate an ereport *and*
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * even if the ereport did arrive we could perform no useful diagnosis
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * e.g., the NB can be configured for sync flood on nb.mem_eccm
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * but we don't choose to discard that ereport here since we could have
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * made a useful diagnosis from it had it been delivered
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * (nb.ht_sync, nb.ht_crc)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * - events that will be accompanied by an immediate panic and
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * delivery of the ereport during subsequent reboot but from
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * which no useful diagnosis can be made. (nb.rmw, nb.wdog)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Ereports for all of these can be generated by error simulation and
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * injection. We will perform a null diagnosos of all these ereports in order
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * to avoid "no subscription" complaints during test harness runs.
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.ma@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.ta@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ls.s_rde@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.ic.rdde@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.bu.s_rde@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.gart_walk@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.ht_sync@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.ht_crc@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.rmw@strand{within(5s)};
e4b86885570d77af552e9cf94f142f4d744fb8c8Cheng Sean Yeevent ereport.cpu.amd.nb.wdog@strand{within(5s)};