199767f8919635c4928607450d9e0abb932109ceToomas Soome * Copyright (c) 2003 Hidetoshi Shimokawa
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
199767f8919635c4928607450d9e0abb932109ceToomas Soome * All rights reserved.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Redistribution and use in source and binary forms, with or without
199767f8919635c4928607450d9e0abb932109ceToomas Soome * modification, are permitted provided that the following conditions
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 1. Redistributions of source code must retain the above copyright
199767f8919635c4928607450d9e0abb932109ceToomas Soome * notice, this list of conditions and the following disclaimer.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 2. Redistributions in binary form must reproduce the above copyright
199767f8919635c4928607450d9e0abb932109ceToomas Soome * notice, this list of conditions and the following disclaimer in the
199767f8919635c4928607450d9e0abb932109ceToomas Soome * documentation and/or other materials provided with the distribution.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 3. All advertising materials mentioning features or use of this software
199767f8919635c4928607450d9e0abb932109ceToomas Soome * must display the acknowledgement as bellow:
199767f8919635c4928607450d9e0abb932109ceToomas Soome * This product includes software developed by K. Kobayashi and H. Shimokawa
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 4. The name of the author may not be used to endorse or promote products
199767f8919635c4928607450d9e0abb932109ceToomas Soome * derived from this software without specific prior written permission.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
199767f8919635c4928607450d9e0abb932109ceToomas Soome * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
199767f8919635c4928607450d9e0abb932109ceToomas Soome * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
199767f8919635c4928607450d9e0abb932109ceToomas Soome * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
199767f8919635c4928607450d9e0abb932109ceToomas Soome * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
199767f8919635c4928607450d9e0abb932109ceToomas Soome * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
199767f8919635c4928607450d9e0abb932109ceToomas Soome * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
199767f8919635c4928607450d9e0abb932109ceToomas Soome * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
199767f8919635c4928607450d9e0abb932109ceToomas Soome * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
199767f8919635c4928607450d9e0abb932109ceToomas Soome * POSSIBILITY OF SUCH DAMAGE.
199767f8919635c4928607450d9e0abb932109ceToomas Soomestatic uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
199767f8919635c4928607450d9e0abb932109ceToomas Soomestatic uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__)
199767f8919635c4928607450d9e0abb932109ceToomas Soome ((((x)<4)? \
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Communication with PHY device
199767f8919635c4928607450d9e0abb932109ceToomas Soomefwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
199767f8919635c4928607450d9e0abb932109ceToomas Soome fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
199767f8919635c4928607450d9e0abb932109ceToomas Soomefwphy_rddata(struct fwohci_softc *sc, u_int addr)
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
199767f8919635c4928607450d9e0abb932109ceToomas Soome for ( i = 0 ; i < MAX_RETRY ; i ++ ){
199767f8919635c4928607450d9e0abb932109ceToomas Soome if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(sc->fc.dev, "phy read failed(1).\n");
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Make sure that SCLK is started */
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(sc->fc.dev, "phy read failed(2).\n");
199767f8919635c4928607450d9e0abb932109ceToomas Soome "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
199767f8919635c4928607450d9e0abb932109ceToomas Soomefwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * probe PHY parameters
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 0. to prove PHY version, whether compliance of 1394a.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 1. to probe maximum speed supported by the PHY and
199767f8919635c4928607450d9e0abb932109ceToomas Soome * number of port supported by core-logic.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * It is not actually available port on your PC .
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(dev, "invalid speed %d (fixed to %d).\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome "Phy 1394 only %s, %d ports.\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(dev, "invalid speed %d (fixed to %d).\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome "Phy 1394a available %s, %d ports.\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* check programPhyEnable */
199767f8919635c4928607450d9e0abb932109ceToomas Soome if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
199767f8919635c4928607450d9e0abb932109ceToomas Soome#else /* XXX force to enable 1394a */
199767f8919635c4928607450d9e0abb932109ceToomas Soome "Enable 1394a Enhancements\n");
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* enable EAA EMC */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* set aPhyEnhanceEnable */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* for safe */
199767f8919635c4928607450d9e0abb932109ceToomas Soomefwohci_reset(struct fwohci_softc *sc, device_t dev)
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Disable interrupts */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* FLUSH FIFO and reset Transmitter/Reciever */
199767f8919635c4928607450d9e0abb932109ceToomas Soome while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
199767f8919635c4928607450d9e0abb932109ceToomas Soome if (i++ > 100) break;
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Probe phy */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Probe link */
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(dev, "Link %s, max_rec %d bytes.\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* XXX fix max_rec */
199767f8919635c4928607450d9e0abb932109ceToomas Soome reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12);
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Initialize registers */
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom));
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Enable link */
199767f8919635c4928607450d9e0abb932109ceToomas Soomefwohci_init(struct fwohci_softc *sc, device_t dev)
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* OHCI version */
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* Available Isochronous DMA channel probe */
199767f8919635c4928607450d9e0abb932109ceToomas Soome reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
199767f8919635c4928607450d9e0abb932109ceToomas Soome for (i = 0; i < 0x20; i++)
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(dev, "No. of Isochronous channels is %d.\n", i);
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* SID recieve buffer must align 2^11 */
199767f8919635c4928607450d9e0abb932109ceToomas Soome sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
199767f8919635c4928607450d9e0abb932109ceToomas Soome for( i = 0 ; i < 8 ; i ++)
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(sc->dev, "Initiate bus reset\n");
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Make sure our cached values from the config rom are
199767f8919635c4928607450d9e0abb932109ceToomas Soome * initialised.
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Set root hold-off bit so that non cyclemaster capable node
199767f8919635c4928607450d9e0abb932109ceToomas Soome * shouldn't became the root node.
199767f8919635c4928607450d9e0abb932109ceToomas Soome#else /* Short bus reset */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Enable bus reset interrupt */
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Allow async. request to us */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* XXX insecure ?? */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Set ATRetries register */
199767f8919635c4928607450d9e0abb932109ceToomas Soome** Checking whether the node is root or not. If root, turn on
199767f8919635c4928607450d9e0abb932109ceToomas Soome** cycle master.
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(sc->dev, "non CYCLEMASTER mode\n");
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(sc->dev, "bus reset phase done\n");
199767f8919635c4928607450d9e0abb932109ceToomas Soomefwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
199767f8919635c4928607450d9e0abb932109ceToomas Soome device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
199767f8919635c4928607450d9e0abb932109ceToomas Soome stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
199767f8919635c4928607450d9e0abb932109ceToomas Soome/* Bus reset */
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Disable bus reset interrupt until sid recv. */
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
199767f8919635c4928607450d9e0abb932109ceToomas Soome OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
199767f8919635c4928607450d9e0abb932109ceToomas Soome } else if (sc->state == FWOHCI_STATE_BUSRESET) {
199767f8919635c4928607450d9e0abb932109ceToomas Soome "device physically ejected?\n");