beripad-de4.dts revision 199767f8919635c4928607450d9e0abb932109ce
/*-
* Copyright (c) 2012-2013 Robert N. M. Watson
* Copyright (c) 2013 SRI International
* All rights reserved.
*
* This software was developed by SRI International and the University of
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Device names here have been largely made up on the spot, especially for the
* "compatible" strings, and might want to be revised.
*
* For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in
* the future, we should likely change to 64-bit.
*/
/ {
compatible = "sri-cambridge,beripad-de4";
cpus {
/*
* Secondary CPUs all start disabled and use the
* spin-table enable method. cpu-release-addr must be
* specified for each cpu other than cpu@0. Values of
* cpu-release-addr grow down from 0x100000 (kernel).
*/
status = "disabled";
cpu@0 {
compatible = "sri-cambridge,beri";
status = "okay";
};
/*
cpu@1 {
device-type = "cpu";
compatible = "sri-cambridge,beri";
reg = <1 1>;
// XXX: should we need cached prefix?
cpu-release-addr = <0xffffffff 0x800fffe0>;
};
*/
};
memory {
device_type = "memory";
};
soc {
/*
* Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
* we use mips4k coprocessor 0 interrupt management directly.
*/
ranges = <>;
compatible = "sri-cambridge,beri-pic";
0x7f806000 0x10
0x7f806080 0x10
0x7f806100 0x10>;
};
compatible = "ns16550";
interrupts = <6>;
};
compatible = "altera,jtag_uart-11_0";
interrupts = <0>;
};
compatible = "altera,jtag_uart-11_0";
};
compatible = "altera,jtag_uart-11_0";
};
compatible = "altera,sdcard_11_2011";
};
compatible = "sri-cambridge,de4led";
};
/*
* XXX-BZ keep flash before ethernet so that atse can read the
* Ethernet addresses for now.
*/
flash@74000000 {
compatible = "cfi-flash";
/* Board configuration */
partition@0 {
label = "config";
};
/* Power up FPGA image */
partition@20000 {
label = "fpga0";
};
/* Secondary FPGA image (on RE_CONFIGn button) */
label = "fpga1";
};
/* Space for operating system use */
partition@1820000 {
label = "os";
};
/* Second stage bootloader */
label = "boot";
};
};
compatible = "altera,atse";
// MAC, RX+RXC, TX+TXC.
0x7f007500 0x8
0x7f007520 0x20
0x7f007400 0x8
0x7f007420 0x20>;
// RX, TX
};
compatible = "altera,atse";
// MAC, RX+RXC, TX+TXC.
0x7f005500 0x8
0x7f005520 0x20
0x7f005400 0x8
0x7f005420 0x20>;
// RX, TX
};
touchscreen@70400000 {
compatible = "sri-cambridge,mtl";
0x70000000 0x177000
0x70177000 0x2000>;
};
usb@0x7f100000 {
compatible = "nxp,usb-isp1761";
0x7f140000 0x4>;
// IRQ 4 is DC, IRQ 5 is HC.
};
avgen@0x7f009000 {
compatible = "sri-cambridge,avgen";
};
avgen@0x7f00a000 {
compatible = "sri-cambridge,avgen";
};
avgen@0x7f00c000 {
compatible = "sri-cambridge,avgen";
};
};
};