zybo.dts revision 199767f8919635c4928607450d9e0abb932109ce
/*-
* Copyright (c) 2015 The FreeBSD Foundation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
model = "zybo";
compatible = "digilent,zybo";
// cpus {
// #address-cells = <1>;
// #size-cells = <0>;
// cpu@0 {
// device-type = "cpu";
// model = "ARM Cortex-A9";
// };
// };
memory {
// First megabyte isn't accessible by all interconnect masters.
device_type = "memory";
};
// Zynq PS System registers.
//
device_type = "soc";
compatible = "simple-bus";
// SLCR block
compatible = "xlnx,zy7_slcr";
};
// Interrupt controller
compatible = "arm,gic";
<0xf00100 0x0100>; // CPU if registers
};
// L2 cache controller
compatible = "arm,pl310";
interrupts = <34>;
};
// Device Config
compatible = "xlnx,zy7_devcfg";
interrupts = <40>;
};
// triple timer counters0,1
compatible = "xlnx,ttc";
};
compatible = "xlnx,ttc";
};
// ARM Cortex A9 TWD Timer
compatible = "arm,mpcore-timers";
<0xf00600 0x20>; // Private Timer Regs
};
// system watch-dog timer
swdt@5000 {
device_type = "watchdog";
compatible = "xlnx,zy7_wdt";
interrupts = <41>;
};
device_type = "watchdog";
compatible = "arm,mpcore_wdt";
interrupts = <30>;
reset = <1>;
};
}; // pssys@f8000000
// Zynq PS I/O Peripheral registers.
//
device_type = "soc";
compatible = "simple-bus";
// uart0: uart@0000 {
// device_type = "serial";
// compatible = "cadence,uart";
// reg = <0x0000 0x1000>;
// interrupts = <59>;
// interrupt-parent = <&GIC>;
// clock-frequency = <50000000>;
// };
device_type = "serial";
compatible = "cadence,uart";
interrupts = <82>;
};
compatible = "xlnx,zy7_gpio";
interrupts = <52>;
};
// GigE
// device_type = "network";
compatible = "cadence,gem";
};
// SDIO
compatible = "xlnx,zy7_sdhci";
interrupts = <56>;
};
// QSPI
compatible = "xlnx,zy7_qspi";
interrupts = <51>;
};
// USB
compatible = "xlnx,zy7_ehci";
interrupts = <53>;
};
}; // ps7io@e0000000
chosen {
};
};