imx51x.dtsi revision 199767f8919635c4928607450d9e0abb932109ce
/*
* Copyright (c) 2012 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Semihalf under sponsorship from
* the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Freescale i.MX515 Device Tree Source.
*
* $FreeBSD$
*/
/ {
aliases {
};
cpus {
cpu@0 {
device_type = "cpu";
compatible = "ARM,MCIMX515";
reg = <0x0>;
/* TODO: describe L2 cache also */
};
};
compatible = "simple-bus";
/* This reflects CPU decode windows setup. */
};
/*
* 60000000 60000FFF 4K Debug ROM
* 60001000 60001FFF 4K ETB
* 60002000 60002FFF 4K ETM
* 60003000 60003FFF 4K TPIU
* 60004000 60004FFF 4K CTI0
* 60005000 60005FFF 4K CTI1
* 60006000 60006FFF 4K CTI2
* 60007000 60007FFF 4K CTI3
* 60008000 60008FFF 4K Cortex Debug Unit
*
* E0000000 E0003FFF 0x4000 TZIC
*/
};
compatible = "simple-bus";
/* Required by many devices, so better to stay first */
/* 73FD4000 0x4000 CCM */
compatible = "fsl,imx51-ccm";
/* 83F80000 0x4000 DPLLIP1 */
/* 83F84000 0x4000 DPLLIP2 */
/* 83F88000 0x4000 DPLLIP3 */
0x83F80000 0x4000
0x83F84000 0x4000
0x83F88000 0x4000>;
status = "disabled";
};
/*
* GPIO modules moved up - to have it attached for
* drivers which rely on GPIO
*/
/* 73F84000 0x4000 GPIO1 */
/* TODO: use <> also */
};
/* 73F88000 0x4000 GPIO2 */
};
/* 73F8C000 0x4000 GPIO3 */
};
/* 73F90000 0x4000 GPIO4 */
};
spba@70000000 {
/* 70004000 0x4000 ESDHC 1 */
esdhc@70004000 {
compatible = "fsl,imx51-esdhc";
status = "disabled";
};
/* 70008000 0x4000 ESDHC 2 */
esdhc@70008000 {
compatible = "fsl,imx51-esdhc";
status = "disabled";
};
/* 7000C000 0x4000 UART 3 */
status = "disabled";
};
/* 70010000 0x4000 eCSPI1 */
ecspi@70010000 {
compatible = "fsl,imx51-ecspi";
status = "disabled";
};
/* 70014000 0x4000 SSI2 irq30 */
compatible = "fsl,imx51-ssi";
status = "disabled";
};
/* 70020000 0x4000 ESDHC 3 */
esdhc@70020000 {
compatible = "fsl,imx51-esdhc";
status = "disabled";
};
/* 70024000 0x4000 ESDHC 4 */
esdhc@70024000 {
compatible = "fsl,imx51-esdhc";
status = "disabled";
};
/* 70028000 0x4000 SPDIF */
/* 91 SPDIF */
/* 70030000 0x4000 PATA (PORT UDMA) irq70 */
/* 70034000 0x4000 SLM */
/* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */
/* 7003C000 0x4000 SPBA */
};
compatible = "usb-nop-xceiv";
status = "okay";
};
interrupts = <18>;
status = "disabled";
};
interrupts = <14>;
status = "disabled";
};
interrupts = <16>;
status = "disabled";
};
interrupts = <17>;
status = "disabled";
};
compatible = "fsl,imx51-usbmisc";
};
/* 73F98000 0x4000 WDOG1 */
status = "disabled";
};
/* 73F9C000 0x4000 WDOG2 (TZ) */
status = "disabled";
};
/* 73F94000 0x4000 KPP */
compatible = "fsl,imx51-kpp";
status = "disabled";
};
/* 73FA0000 0x4000 GPT */
compatible = "fsl,imx51-gpt";
status = "disabled";
};
/* 73FA4000 0x4000 SRTC */
compatible = "fsl,imx51-srtc";
status = "disabled";
};
/* 73FA8000 0x4000 IOMUXC */
compatible = "fsl,imx51-iomux";
};
/* 73FAC000 0x4000 EPIT1 */
compatible = "fsl,imx51-epit";
status = "disabled";
};
/* 73FB0000 0x4000 EPIT2 */
compatible = "fsl,imx51-epit";
status = "disabled";
};
/* 73FB4000 0x4000 PWM1 */
compatible = "fsl,imx51-pwm";
status = "disabled";
};
/* 73FB8000 0x4000 PWM2 */
compatible = "fsl,imx51-pwm";
status = "disabled";
};
/* 73FBC000 0x4000 UART 1 */
status = "disabled";
};
/* 73FC0000 0x4000 UART 2 */
status = "disabled";
};
/* 73FC4000 0x4000 USBOH3 */
/* NOTYET
usb@73fc4000 {
compatible = "fsl,imx51-otg";
reg = <0x73fc4000 0x4000>;
interrupt-parent = <&tzic>; interrupts = <>;
status = "disabled";
};
*/
/* 73FD0000 0x4000 SRC */
compatible = "fsl,imx51-src";
status = "disabled";
};
/* 73FD8000 0x4000 GPC */
compatible = "fsl,imx51-gpc";
status = "disabled";
};
};
/* 83F94000 0x4000 AHBMAX */
/* 83F98000 0x4000 IIM */
/*
* 69 IIM Interrupt request to the processor.
* Indicates to the processor that program or
* explicit.
*/
/* 83F9C000 0x4000 CSU */
/*
* 27 CSU Interrupt Request 1. Indicates to the
* processor that one or more alarm inputs were.
*/
/* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
/* irq76 Neon Monitor Interrupt */
/* irq77 Performance Unit Interrupt */
/* irq78 CTI IRQ */
/* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
/* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
/* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
/* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
/* 83FA4000 0x4000 OWIRE irq88 */
/* 83FA8000 0x4000 FIRI irq93 */
/* 83FAC000 0x4000 eCSPI2 */
compatible = "fsl,imx51-ecspi";
status = "disabled";
};
/* 83FB0000 0x4000 SDMA */
};
/* 83FB4000 0x4000 SCC */
/* 21 SCC Security Monitor High Priority Interrupt. */
/* 22 SCC Secure (TrustZone) Interrupt. */
/* 23 SCC Regular (Non-Secure) Interrupt. */
/* 83FB8000 0x4000 ROMCP */
/* 83FBC000 0x4000 RTIC */
/*
* 26 RTIC RTIC (Trust Zone) Interrupt Request.
* Indicates that the RTIC has completed hashing the
*/
/* 83FC0000 0x4000 CSPI */
status = "disabled";
};
/* 83FC4000 0x4000 I2C2 */
status = "disabled";
};
/* 83FC8000 0x4000 I2C1 */
status = "disabled";
};
/* 83FCC000 0x4000 SSI1 */
/* 29 SSI1 SSI-1 Interrupt Request */
compatible = "fsl,imx51-ssi";
status = "disabled";
};
/* 83FD0000 0x4000 AUDMUX */
compatible = "fsl,imx51-audmux";
status = "disabled";
};
/* 83FD8000 0x4000 EMI1 */
/* 8 EMI (NFC) */
/* 15 EMI */
/* 97 EMI Boot sequence completed interrupt */
/*
* 101 EMI Indicates all pages have been transferred
* to NFC during an auto program operation.
*/
/* 83FE0000 0x4000 PATA (PORT PIO) */
/* 70 PATA Parallel ATA host controller interrupt */
compatible = "fsl,imx51-ata";
interrupts = <70>;
status = "disabled";
};
/* 83FE4000 0x4000 SIM */
/* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */
/* 68 SIM intr composed of tc, etc, tfe, and rdrf */
/* 83FE8000 0x4000 SSI3 */
/* 96 SSI3 SSI-3 Interrupt Request */
compatible = "fsl,imx51-ssi";
status = "disabled";
};
/* 83FEC000 0x4000 FEC */
compatible = "fsl,imx51-fec";
status = "disabled";
};
/* 83FF0000 0x4000 TVE */
/* 92 TVE */
/* 83FF4000 0x4000 VPU */
/* 9 VPU */
/* 100 VPU Idle interrupt from VPU */
/* 83FF8000 0x4000 SAHARA Lite */
/* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */
/* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr Lite */
};
};
localbus@5e000000 {
compatible = "simple-bus";
compatible = "fsl,ipu3";
reg = <
0x5e000000 0x08000 /* CM */
0x5e008000 0x08000 /* IDMAC */
0x5e018000 0x08000 /* DP */
0x5e020000 0x08000 /* IC */
0x5e028000 0x08000 /* IRT */
0x5e030000 0x08000 /* CSI0 */
0x5e038000 0x08000 /* CSI1 */
0x5e040000 0x08000 /* DI0 */
0x5e048000 0x08000 /* DI1 */
0x5e050000 0x08000 /* SMFC */
0x5e058000 0x08000 /* DC */
0x5e060000 0x08000 /* DMFC */
0x5e068000 0x08000 /* VDI */
0x5f000000 0x20000 /* CPMEM */
0x5f020000 0x20000 /* LUT */
0x5f040000 0x20000 /* SRM */
0x5f060000 0x20000 /* TPM */
0x5f080000 0x20000 /* DCTMPL */
>;
interrupts = <
10 /* IPUEX Error */
11 /* IPUEX Sync */
>;
status = "disabled";
};
};
};
/*
TODO: Not mapped interrupts
5 DAP
84 GPU2D (OpenVG) general interrupt
85 GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
12 GPU3D
102 GPU3D Idle interrupt from GPU3D (for S/W power gating)
90 SJC
*/