at91rm9200_lowlevel.c revision 199767f8919635c4928607450d9e0abb932109ce
/*-
* Copyright (c) 2006 M. Warner Losh. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* This software is derived from software provide by Kwikbyte who specifically
* disclaimed copyright on the code.
*
* $FreeBSD$
*/
#include "at91rm9200.h"
#include "at91rm9200_lowlevel.h"
extern int __bss_start__[];
extern int __bss_end__[];
#define BAUD 115200
/*
* void DefaultSystemInit(void)
* Load the system with sane values based on how the system is configured.
* at91rm9200_lowlevel.h is expected to define the necessary parameters.
*/
void
_init(void)
{
int *i;
register unsigned value;
#ifdef BOOT_TSC
// For the TSC board, we turn ON the one LED we have while
// early in boot.
#endif
#if defined(BOOT_KB920X)
#endif
// configure clocks
// assume:
// main osc = 10Mhz
// PLLB configured for 96MHz (48MHz after div)
// CSS = PLLB
// set PLLA = 180MHz
// assume main osc = 10Mhz
// div = 5 , out = 2 (150MHz = 240MHz)
// wait for lock
continue;
// change divider = 3, pres = 1
// wait for update
continue;
// change CSS = PLLA
value &= ~AT91C_PMC_CSS;
// wait for update
continue;
#ifdef BOOT_KB920X
// setup flash access (allow ample margin)
// 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device
(9 & AT91C_SMC2_NWS) |
#endif
// setup SDRAM access
// EBI chip-select register (CS1 = SDRAM controller)
// 9 col, 13row, 4 bank, CAS2
// write recovery = 2 (Twr)
// row cycle = 5 (Trc)
// precharge delay = 2 (Trp)
// row to col delay 2 (Trcd)
// active to precharge = 4 (Tras)
// exit self refresh to active = 6 (Txsr)
value &= ~AT91C_EBI_CS1A;
#if defined(KB9202_B) || defined(SDRAM_128M)
#else
#endif
// Step 1: We assume 200us of idle time.
// Step 2: Issue an all banks precharge command
*p = 0;
// Step 3: Issue 8 Auto-refresh (CBR) cycles
*p = 0;
*p = 0;
*p = 0;
*p = 0;
*p = 0;
*p = 0;
*p = 0;
*p = 0;
// Step 4: Issue an Mode Set Register (MRS) cycle to program in
// the parameters that we setup in the SDRC_CR register above.
*p = 0;
// Step 5: set the refresh timer and access memory to start it
// running. We have to wait 3 clocks after the LMR_CMD above,
// and this fits the bill nicely.
*p = 0;
// Step 6: Set normal mode.
*p = 0;
// Turn on the upper 16 bits on the SDRAM bus.
#endif
// Configure DBGU -use local routine optimized for space
/* Zero BSS now that we have memory setup */
i = (int *)__bss_start__;
while (i < (int *)__bss_end__)
*i++ = 0;
}