199767f8919635c4928607450d9e0abb932109ceToomas Soome * Copyright (c) 2006 M. Warner Losh. All rights reserved.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Redistribution and use in source and binary forms, with or without
199767f8919635c4928607450d9e0abb932109ceToomas Soome * modification, are permitted provided that the following conditions
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 1. Redistributions of source code must retain the above copyright
199767f8919635c4928607450d9e0abb932109ceToomas Soome * notice, this list of conditions and the following disclaimer.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * 2. Redistributions in binary form must reproduce the above copyright
199767f8919635c4928607450d9e0abb932109ceToomas Soome * notice, this list of conditions and the following disclaimer in the
199767f8919635c4928607450d9e0abb932109ceToomas Soome * documentation and/or other materials provided with the distribution.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
199767f8919635c4928607450d9e0abb932109ceToomas Soome * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
199767f8919635c4928607450d9e0abb932109ceToomas Soome * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
199767f8919635c4928607450d9e0abb932109ceToomas Soome * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
199767f8919635c4928607450d9e0abb932109ceToomas Soome * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
199767f8919635c4928607450d9e0abb932109ceToomas Soome * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
199767f8919635c4928607450d9e0abb932109ceToomas Soome * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
199767f8919635c4928607450d9e0abb932109ceToomas Soome * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
199767f8919635c4928607450d9e0abb932109ceToomas Soome * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * This software is derived from software provide by Kwikbyte who specifically
199767f8919635c4928607450d9e0abb932109ceToomas Soome * disclaimed copyright on the code.
199767f8919635c4928607450d9e0abb932109ceToomas Soome#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * void DefaultSystemInit(void)
199767f8919635c4928607450d9e0abb932109ceToomas Soome * Load the system with sane values based on how the system is configured.
199767f8919635c4928607450d9e0abb932109ceToomas Soome * at91rm9200_lowlevel.h is expected to define the necessary parameters.
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
199767f8919635c4928607450d9e0abb932109ceToomas Soome volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE;
199767f8919635c4928607450d9e0abb932109ceToomas Soome // For the TSC board, we turn ON the one LED we have while
199767f8919635c4928607450d9e0abb932109ceToomas Soome // early in boot.
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
199767f8919635c4928607450d9e0abb932109ceToomas Soome // configure clocks
199767f8919635c4928607450d9e0abb932109ceToomas Soome // main osc = 10Mhz
199767f8919635c4928607450d9e0abb932109ceToomas Soome // PLLB configured for 96MHz (48MHz after div)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // CSS = PLLB
199767f8919635c4928607450d9e0abb932109ceToomas Soome // set PLLA = 180MHz
199767f8919635c4928607450d9e0abb932109ceToomas Soome // assume main osc = 10Mhz
199767f8919635c4928607450d9e0abb932109ceToomas Soome // div = 5 , out = 2 (150MHz = 240MHz)
199767f8919635c4928607450d9e0abb932109ceToomas Soome value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA);
199767f8919635c4928607450d9e0abb932109ceToomas Soome value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA |
199767f8919635c4928607450d9e0abb932109ceToomas Soome // wait for lock
199767f8919635c4928607450d9e0abb932109ceToomas Soome while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA))
199767f8919635c4928607450d9e0abb932109ceToomas Soome // change divider = 3, pres = 1
199767f8919635c4928607450d9e0abb932109ceToomas Soome value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK;
199767f8919635c4928607450d9e0abb932109ceToomas Soome // wait for update
199767f8919635c4928607450d9e0abb932109ceToomas Soome while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
199767f8919635c4928607450d9e0abb932109ceToomas Soome // change CSS = PLLA
199767f8919635c4928607450d9e0abb932109ceToomas Soome // wait for update
199767f8919635c4928607450d9e0abb932109ceToomas Soome while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
199767f8919635c4928607450d9e0abb932109ceToomas Soome // setup flash access (allow ample margin)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device
199767f8919635c4928607450d9e0abb932109ceToomas Soome // setup SDRAM access
199767f8919635c4928607450d9e0abb932109ceToomas Soome // EBI chip-select register (CS1 = SDRAM controller)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // 9 col, 13row, 4 bank, CAS2
199767f8919635c4928607450d9e0abb932109ceToomas Soome // write recovery = 2 (Twr)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // row cycle = 5 (Trc)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // precharge delay = 2 (Trp)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // row to col delay 2 (Trcd)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // active to precharge = 4 (Tras)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // exit self refresh to active = 6 (Txsr)
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Step 1: We assume 200us of idle time.
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Step 2: Issue an all banks precharge command
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD;
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Step 3: Issue 8 Auto-refresh (CBR) cycles
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD;
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Step 4: Issue an Mode Set Register (MRS) cycle to program in
199767f8919635c4928607450d9e0abb932109ceToomas Soome // the parameters that we setup in the SDRC_CR register above.
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD;
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Step 5: set the refresh timer and access memory to start it
199767f8919635c4928607450d9e0abb932109ceToomas Soome // running. We have to wait 3 clocks after the LMR_CMD above,
199767f8919635c4928607450d9e0abb932109ceToomas Soome // and this fits the bill nicely.
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000;
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Step 6: Set normal mode.
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD;
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Turn on the upper 16 bits on the SDRAM bus.
199767f8919635c4928607450d9e0abb932109ceToomas Soome // Configure DBGU -use local routine optimized for space
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA31 | AT91C_PIO_PA30;
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_BASE_PIOA->PIO_PDR = AT91C_PIO_PA31 | AT91C_PIO_PA30;
199767f8919635c4928607450d9e0abb932109ceToomas Soome AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
199767f8919635c4928607450d9e0abb932109ceToomas Soome pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10);
199767f8919635c4928607450d9e0abb932109ceToomas Soome /* Zero BSS now that we have memory setup */
199767f8919635c4928607450d9e0abb932109ceToomas Soome while (i < (int *)__bss_end__)