#ifndef AT91RM9200_H

#define AT91RM9200_H

#define ATMEL_ENV

typedef volatile unsigned int AT91_REG;// Hardware register definition

typedef struct _AT91S_SYS {

AT91_REG AIC_SMR[32]; // Source Mode Register

AT91_REG AIC_SVR[32]; // Source Vector Register

AT91_REG AIC_IVR; // IRQ Vector Register

AT91_REG AIC_FVR; // FIQ Vector Register

AT91_REG AIC_ISR; // Interrupt Status Register

AT91_REG AIC_IPR; // Interrupt Pending Register

AT91_REG AIC_IMR; // Interrupt Mask Register

AT91_REG AIC_CISR; // Core Interrupt Status Register

AT91_REG Reserved0[2]; //

AT91_REG AIC_IECR; // Interrupt Enable Command Register

AT91_REG AIC_IDCR; // Interrupt Disable Command Register

AT91_REG AIC_ICCR; // Interrupt Clear Command Register

AT91_REG AIC_ISCR; // Interrupt Set Command Register

AT91_REG AIC_EOICR; // End of Interrupt Command Register

AT91_REG AIC_SPU; // Spurious Vector Register

AT91_REG AIC_DCR; // Debug Control Register (Protect)

AT91_REG Reserved1[1]; //

AT91_REG AIC_FFER; // Fast Forcing Enable Register

AT91_REG AIC_FFDR; // Fast Forcing Disable Register

AT91_REG AIC_FFSR; // Fast Forcing Status Register

AT91_REG Reserved2[45]; //

AT91_REG DBGU_CR; // Control Register

AT91_REG DBGU_MR; // Mode Register

AT91_REG DBGU_IER; // Interrupt Enable Register

AT91_REG DBGU_IDR; // Interrupt Disable Register

AT91_REG DBGU_IMR; // Interrupt Mask Register

AT91_REG DBGU_CSR; // Channel Status Register

AT91_REG DBGU_RHR; // Receiver Holding Register

AT91_REG DBGU_THR; // Transmitter Holding Register

AT91_REG DBGU_BRGR; // Baud Rate Generator Register

AT91_REG Reserved3[7]; //

AT91_REG DBGU_C1R; // Chip ID1 Register

AT91_REG DBGU_C2R; // Chip ID2 Register

AT91_REG DBGU_FNTR; // Force NTRST Register

AT91_REG Reserved4[45]; //

AT91_REG DBGU_RPR; // Receive Pointer Register

AT91_REG DBGU_RCR; // Receive Counter Register

AT91_REG DBGU_TPR; // Transmit Pointer Register

AT91_REG DBGU_TCR; // Transmit Counter Register

AT91_REG DBGU_RNPR; // Receive Next Pointer Register

AT91_REG DBGU_RNCR; // Receive Next Counter Register

AT91_REG DBGU_TNPR; // Transmit Next Pointer Register

AT91_REG DBGU_TNCR; // Transmit Next Counter Register

AT91_REG DBGU_PTCR; // PDC Transfer Control Register

AT91_REG DBGU_PTSR; // PDC Transfer Status Register

AT91_REG Reserved5[54]; //

AT91_REG PIOA_PER; // PIO Enable Register

AT91_REG PIOA_PDR; // PIO Disable Register

AT91_REG PIOA_PSR; // PIO Status Register

AT91_REG Reserved6[1]; //

AT91_REG PIOA_OER; // Output Enable Register

AT91_REG PIOA_ODR; // Output Disable Registerr

AT91_REG PIOA_OSR; // Output Status Register

AT91_REG Reserved7[1]; //

AT91_REG PIOA_IFER; // Input Filter Enable Register

AT91_REG PIOA_IFDR; // Input Filter Disable Register

AT91_REG PIOA_IFSR; // Input Filter Status Register

AT91_REG Reserved8[1]; //

AT91_REG PIOA_SODR; // Set Output Data Register

AT91_REG PIOA_CODR; // Clear Output Data Register

AT91_REG PIOA_ODSR; // Output Data Status Register

AT91_REG PIOA_PDSR; // Pin Data Status Register

AT91_REG PIOA_IER; // Interrupt Enable Register

AT91_REG PIOA_IDR; // Interrupt Disable Register

AT91_REG PIOA_IMR; // Interrupt Mask Register

AT91_REG PIOA_ISR; // Interrupt Status Register

AT91_REG PIOA_MDER; // Multi-driver Enable Register

AT91_REG PIOA_MDDR; // Multi-driver Disable Register

AT91_REG PIOA_MDSR; // Multi-driver Status Register

AT91_REG Reserved9[1]; //

AT91_REG PIOA_PPUDR; // Pull-up Disable Register

AT91_REG PIOA_PPUER; // Pull-up Enable Register

AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register

AT91_REG Reserved10[1]; //

AT91_REG PIOA_ASR; // Select A Register

AT91_REG PIOA_BSR; // Select B Register

AT91_REG PIOA_ABSR; // AB Select Status Register

AT91_REG Reserved11[9]; //

AT91_REG PIOA_OWER; // Output Write Enable Register

AT91_REG PIOA_OWDR; // Output Write Disable Register

AT91_REG PIOA_OWSR; // Output Write Status Register

AT91_REG Reserved12[85]; //

AT91_REG PIOB_PER; // PIO Enable Register

AT91_REG PIOB_PDR; // PIO Disable Register

AT91_REG PIOB_PSR; // PIO Status Register

AT91_REG Reserved13[1]; //

AT91_REG PIOB_OER; // Output Enable Register

AT91_REG PIOB_ODR; // Output Disable Registerr

AT91_REG PIOB_OSR; // Output Status Register

AT91_REG Reserved14[1]; //

AT91_REG PIOB_IFER; // Input Filter Enable Register

AT91_REG PIOB_IFDR; // Input Filter Disable Register

AT91_REG PIOB_IFSR; // Input Filter Status Register

AT91_REG Reserved15[1]; //

AT91_REG PIOB_SODR; // Set Output Data Register

AT91_REG PIOB_CODR; // Clear Output Data Register

AT91_REG PIOB_ODSR; // Output Data Status Register

AT91_REG PIOB_PDSR; // Pin Data Status Register

AT91_REG PIOB_IER; // Interrupt Enable Register

AT91_REG PIOB_IDR; // Interrupt Disable Register

AT91_REG PIOB_IMR; // Interrupt Mask Register

AT91_REG PIOB_ISR; // Interrupt Status Register

AT91_REG PIOB_MDER; // Multi-driver Enable Register

AT91_REG PIOB_MDDR; // Multi-driver Disable Register

AT91_REG PIOB_MDSR; // Multi-driver Status Register

AT91_REG Reserved16[1]; //

AT91_REG PIOB_PPUDR; // Pull-up Disable Register

AT91_REG PIOB_PPUER; // Pull-up Enable Register

AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register

AT91_REG Reserved17[1]; //

AT91_REG PIOB_ASR; // Select A Register

AT91_REG PIOB_BSR; // Select B Register

AT91_REG PIOB_ABSR; // AB Select Status Register

AT91_REG Reserved18[9]; //

AT91_REG PIOB_OWER; // Output Write Enable Register

AT91_REG PIOB_OWDR; // Output Write Disable Register

AT91_REG PIOB_OWSR; // Output Write Status Register

AT91_REG Reserved19[85]; //

AT91_REG PIOC_PER; // PIO Enable Register

AT91_REG PIOC_PDR; // PIO Disable Register

AT91_REG PIOC_PSR; // PIO Status Register

AT91_REG Reserved20[1]; //

AT91_REG PIOC_OER; // Output Enable Register

AT91_REG PIOC_ODR; // Output Disable Registerr

AT91_REG PIOC_OSR; // Output Status Register

AT91_REG Reserved21[1]; //

AT91_REG PIOC_IFER; // Input Filter Enable Register

AT91_REG PIOC_IFDR; // Input Filter Disable Register

AT91_REG PIOC_IFSR; // Input Filter Status Register

AT91_REG Reserved22[1]; //

AT91_REG PIOC_SODR; // Set Output Data Register

AT91_REG PIOC_CODR; // Clear Output Data Register

AT91_REG PIOC_ODSR; // Output Data Status Register

AT91_REG PIOC_PDSR; // Pin Data Status Register

AT91_REG PIOC_IER; // Interrupt Enable Register

AT91_REG PIOC_IDR; // Interrupt Disable Register

AT91_REG PIOC_IMR; // Interrupt Mask Register

AT91_REG PIOC_ISR; // Interrupt Status Register

AT91_REG PIOC_MDER; // Multi-driver Enable Register

AT91_REG PIOC_MDDR; // Multi-driver Disable Register

AT91_REG PIOC_MDSR; // Multi-driver Status Register

AT91_REG Reserved23[1]; //

AT91_REG PIOC_PPUDR; // Pull-up Disable Register

AT91_REG PIOC_PPUER; // Pull-up Enable Register

AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register

AT91_REG Reserved24[1]; //

AT91_REG PIOC_ASR; // Select A Register

AT91_REG PIOC_BSR; // Select B Register

AT91_REG PIOC_ABSR; // AB Select Status Register

AT91_REG Reserved25[9]; //

AT91_REG PIOC_OWER; // Output Write Enable Register

AT91_REG PIOC_OWDR; // Output Write Disable Register

AT91_REG PIOC_OWSR; // Output Write Status Register

AT91_REG Reserved26[85]; //

AT91_REG PIOD_PER; // PIO Enable Register

AT91_REG PIOD_PDR; // PIO Disable Register

AT91_REG PIOD_PSR; // PIO Status Register

AT91_REG Reserved27[1]; //

AT91_REG PIOD_OER; // Output Enable Register

AT91_REG PIOD_ODR; // Output Disable Registerr

AT91_REG PIOD_OSR; // Output Status Register

AT91_REG Reserved28[1]; //

AT91_REG PIOD_IFER; // Input Filter Enable Register

AT91_REG PIOD_IFDR; // Input Filter Disable Register

AT91_REG PIOD_IFSR; // Input Filter Status Register

AT91_REG Reserved29[1]; //

AT91_REG PIOD_SODR; // Set Output Data Register

AT91_REG PIOD_CODR; // Clear Output Data Register

AT91_REG PIOD_ODSR; // Output Data Status Register

AT91_REG PIOD_PDSR; // Pin Data Status Register

AT91_REG PIOD_IER; // Interrupt Enable Register

AT91_REG PIOD_IDR; // Interrupt Disable Register

AT91_REG PIOD_IMR; // Interrupt Mask Register

AT91_REG PIOD_ISR; // Interrupt Status Register

AT91_REG PIOD_MDER; // Multi-driver Enable Register

AT91_REG PIOD_MDDR; // Multi-driver Disable Register

AT91_REG PIOD_MDSR; // Multi-driver Status Register

AT91_REG Reserved30[1]; //

AT91_REG PIOD_PPUDR; // Pull-up Disable Register

AT91_REG PIOD_PPUER; // Pull-up Enable Register

AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register

AT91_REG Reserved31[1]; //

AT91_REG PIOD_ASR; // Select A Register

AT91_REG PIOD_BSR; // Select B Register

AT91_REG PIOD_ABSR; // AB Select Status Register

AT91_REG Reserved32[9]; //

AT91_REG PIOD_OWER; // Output Write Enable Register

AT91_REG PIOD_OWDR; // Output Write Disable Register

AT91_REG PIOD_OWSR; // Output Write Status Register

AT91_REG Reserved33[85]; //

AT91_REG PMC_SCER; // System Clock Enable Register

AT91_REG PMC_SCDR; // System Clock Disable Register

AT91_REG PMC_SCSR; // System Clock Status Register

AT91_REG Reserved34[1]; //

AT91_REG PMC_PCER; // Peripheral Clock Enable Register

AT91_REG PMC_PCDR; // Peripheral Clock Disable Register

AT91_REG PMC_PCSR; // Peripheral Clock Status Register

AT91_REG Reserved35[1]; //

AT91_REG CKGR_MOR; // Main Oscillator Register

AT91_REG CKGR_MCFR; // Main Clock Frequency Register

AT91_REG CKGR_PLLAR; // PLL A Register

AT91_REG CKGR_PLLBR; // PLL B Register

AT91_REG PMC_MCKR; // Master Clock Register

AT91_REG Reserved36[3]; //

AT91_REG PMC_PCKR[8]; // Programmable Clock Register

AT91_REG PMC_IER; // Interrupt Enable Register

AT91_REG PMC_IDR; // Interrupt Disable Register

AT91_REG PMC_SR; // Status Register

AT91_REG PMC_IMR; // Interrupt Mask Register

AT91_REG Reserved37[36]; //

AT91_REG ST_CR; // Control Register

AT91_REG ST_PIMR; // Period Interval Mode Register

AT91_REG ST_WDMR; // Watchdog Mode Register

AT91_REG ST_RTMR; // Real-time Mode Register

AT91_REG ST_SR; // Status Register

AT91_REG ST_IER; // Interrupt Enable Register

AT91_REG ST_IDR; // Interrupt Disable Register

AT91_REG ST_IMR; // Interrupt Mask Register

AT91_REG ST_RTAR; // Real-time Alarm Register

AT91_REG ST_CRTR; // Current Real-time Register

AT91_REG Reserved38[54]; //

AT91_REG RTC_CR; // Control Register

AT91_REG RTC_MR; // Mode Register

AT91_REG RTC_TIMR; // Time Register

AT91_REG RTC_CALR; // Calendar Register

AT91_REG RTC_TIMALR; // Time Alarm Register

AT91_REG RTC_CALALR; // Calendar Alarm Register

AT91_REG RTC_SR; // Status Register

AT91_REG RTC_SCCR; // Status Clear Command Register

AT91_REG RTC_IER; // Interrupt Enable Register

AT91_REG RTC_IDR; // Interrupt Disable Register

AT91_REG RTC_IMR; // Interrupt Mask Register

AT91_REG RTC_VER; // Valid Entry Register

AT91_REG Reserved39[52]; //

AT91_REG MC_RCR; // MC Remap Control Register

AT91_REG MC_ASR; // MC Abort Status Register

AT91_REG MC_AASR; // MC Abort Address Status Register

AT91_REG Reserved40[1]; //

AT91_REG MC_PUIA[16]; // MC Protection Unit Area

AT91_REG MC_PUP; // MC Protection Unit Peripherals

AT91_REG MC_PUER; // MC Protection Unit Enable Register

AT91_REG Reserved41[2]; //

AT91_REG EBI_CSA; // Chip Select Assignment Register

AT91_REG EBI_CFGR; // Configuration Register

AT91_REG Reserved42[2]; //

AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register

AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register

AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register

AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register

AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register

AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register

AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register

AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register

AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register

AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register

AT91_REG Reserved43[3]; //

AT91_REG EBI_BFC_MR; // BFC Mode Register

} AT91S_SYS, *AT91PS_SYS;

typedef struct _AT91S_MC {

AT91_REG MC_RCR; // MC Remap Control Register

AT91_REG MC_ASR; // MC Abort Status Register

AT91_REG MC_AASR; // MC Abort Address Status Register

AT91_REG Reserved0[1]; //

AT91_REG MC_PUIA[16]; // MC Protection Unit Area

AT91_REG MC_PUP; // MC Protection Unit Peripherals

AT91_REG MC_PUER; // MC Protection Unit Enable Register

} AT91S_MC, *AT91PS_MC;

#define AT91C_MC_RCB (0x1u << 0) // (MC) Remap Command Bit

#define AT91C_MC_UNDADD (0x1u << 0) // (MC) Undefined Addess Abort Status

#define AT91C_MC_MISADD (0x1u << 1) // (MC) Misaligned Addess Abort Status

#define AT91C_MC_MPU (0x1u << 2) // (MC) Memory protection Unit Abort Status

#define AT91C_MC_ABTSZ (0x3u << 8) // (MC) Abort Size Status

#define AT91C_MC_ABTSZ_BYTE (0x0u << 8) // (MC) Byte

#define AT91C_MC_ABTSZ_HWORD (0x1u << 8) // (MC) Half-word

#define AT91C_MC_ABTSZ_WORD (0x2u << 8) // (MC) Word

#define AT91C_MC_ABTTYP (0x3u << 10) // (MC) Abort Type Status

#define AT91C_MC_ABTTYP_DATAR (0x0u << 10) // (MC) Data Read

#define AT91C_MC_ABTTYP_DATAW (0x1u << 10) // (MC) Data Write

#define AT91C_MC_ABTTYP_FETCH (0x2u << 10) // (MC) Code Fetch

#define AT91C_MC_MST0 (0x1u << 16) // (MC) Master 0 Abort Source

#define AT91C_MC_MST1 (0x1u << 17) // (MC) Master 1 Abort Source

#define AT91C_MC_SVMST0 (0x1u << 24) // (MC) Saved Master 0 Abort Source

#define AT91C_MC_SVMST1 (0x1u << 25) // (MC) Saved Master 1 Abort Source

#define AT91C_MC_PROT (0x3u << 0) // (MC) Protection

#define AT91C_MC_PROT_PNAUNA 0x0u // (MC) Privilege: No Access, User: No Access

#define AT91C_MC_PROT_PRWUNA 0x1u // (MC) Privilege: Read/Write, User: No Access

#define AT91C_MC_PROT_PRWURO 0x2u // (MC) Privilege: Read/Write, User: Read Only

#define AT91C_MC_PROT_PRWURW 0x3u // (MC) Privilege: Read/Write, User: Read/Write

#define AT91C_MC_SIZE (0xFu << 4) // (MC) Internal Area Size

#define AT91C_MC_SIZE_1KB (0x0u << 4) // (MC) Area size 1KByte

#define AT91C_MC_SIZE_2KB (0x1u << 4) // (MC) Area size 2KByte

#define AT91C_MC_SIZE_4KB (0x2u << 4) // (MC) Area size 4KByte

#define AT91C_MC_SIZE_8KB (0x3u << 4) // (MC) Area size 8KByte

#define AT91C_MC_SIZE_16KB (0x4u << 4) // (MC) Area size 16KByte

#define AT91C_MC_SIZE_32KB (0x5u << 4) // (MC) Area size 32KByte

#define AT91C_MC_SIZE_64KB (0x6u << 4) // (MC) Area size 64KByte

#define AT91C_MC_SIZE_128KB (0x7u << 4) // (MC) Area size 128KByte

#define AT91C_MC_SIZE_256KB (0x8u << 4) // (MC) Area size 256KByte

#define AT91C_MC_SIZE_512KB (0x9u << 4) // (MC) Area size 512KByte

#define AT91C_MC_SIZE_1MB (0xAu << 4) // (MC) Area size 1MByte

#define AT91C_MC_SIZE_2MB (0xBu << 4) // (MC) Area size 2MByte

#define AT91C_MC_SIZE_4MB (0xCu << 4) // (MC) Area size 4MByte

#define AT91C_MC_SIZE_8MB (0xDu << 4) // (MC) Area size 8MByte

#define AT91C_MC_SIZE_16MB (0xEu << 4) // (MC) Area size 16MByte

#define AT91C_MC_SIZE_64MB (0xFu << 4) // (MC) Area size 64MByte

#define AT91C_MC_BA (0x3FFFFu << 10) // (MC) Internal Area Base Address

#define AT91C_MC_PUEB (0x1u << 0) // (MC) Protection Unit enable Bit

typedef struct _AT91S_RTC {

AT91_REG RTC_CR; // Control Register

AT91_REG RTC_MR; // Mode Register

AT91_REG RTC_TIMR; // Time Register

AT91_REG RTC_CALR; // Calendar Register

AT91_REG RTC_TIMALR; // Time Alarm Register

AT91_REG RTC_CALALR; // Calendar Alarm Register

AT91_REG RTC_SR; // Status Register

AT91_REG RTC_SCCR; // Status Clear Command Register

AT91_REG RTC_IER; // Interrupt Enable Register

AT91_REG RTC_IDR; // Interrupt Disable Register

AT91_REG RTC_IMR; // Interrupt Mask Register

AT91_REG RTC_VER; // Valid Entry Register

} AT91S_RTC, *AT91PS_RTC;

#define AT91C_RTC_UPDTIM (0x1u << 0) // (RTC) Update Request Time Register

#define AT91C_RTC_UPDCAL (0x1u << 1) // (RTC) Update Request Calendar Register

#define AT91C_RTC_TIMEVSEL (0x3u << 8) // (RTC) Time Event Selection

#define AT91C_RTC_TIMEVSEL_MINUTE (0x0u << 8) // (RTC) Minute change.

#define AT91C_RTC_TIMEVSEL_HOUR (0x1u << 8) // (RTC) Hour change.

#define AT91C_RTC_TIMEVSEL_DAY24 (0x2u << 8) // (RTC) Every day at midnight.

#define AT91C_RTC_TIMEVSEL_DAY12 (0x3u << 8) // (RTC) Every day at noon.

#define AT91C_RTC_CALEVSEL (0x3u << 16) // (RTC) Calendar Event Selection

#define AT91C_RTC_CALEVSEL_WEEK (0x0u << 16) // (RTC) Week change (every Monday at time 00:00:00).

#define AT91C_RTC_CALEVSEL_MONTH (0x1u << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).

#define AT91C_RTC_CALEVSEL_YEAR (0x2u << 16) // (RTC) Year change (every January 1 at time 00:00:00).

#define AT91C_RTC_HRMOD (0x1u << 0) // (RTC) 12-24 hour Mode

#define AT91C_RTC_SEC (0x7Fu << 0) // (RTC) Current Second

#define AT91C_RTC_MIN (0x7Fu << 8) // (RTC) Current Minute

#define AT91C_RTC_HOUR (0x1Fu << 16) // (RTC) Current Hour

#define AT91C_RTC_AMPM (0x1u << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator

#define AT91C_RTC_CENT (0x3Fu << 0) // (RTC) Current Century

#define AT91C_RTC_YEAR (0xFFu << 8) // (RTC) Current Year

#define AT91C_RTC_MONTH (0x1Fu << 16) // (RTC) Current Month

#define AT91C_RTC_DAY (0x7u << 21) // (RTC) Current Day

#define AT91C_RTC_DATE (0x3Fu << 24) // (RTC) Current Date

#define AT91C_RTC_SECEN (0x1u << 7) // (RTC) Second Alarm Enable

#define AT91C_RTC_MINEN (0x1u << 15) // (RTC) Minute Alarm

#define AT91C_RTC_HOUREN (0x1u << 23) // (RTC) Current Hour

#define AT91C_RTC_MONTHEN (0x1u << 23) // (RTC) Month Alarm Enable

#define AT91C_RTC_DATEEN (0x1u << 31) // (RTC) Date Alarm Enable

#define AT91C_RTC_ACKUPD (0x1u << 0) // (RTC) Acknowledge for Update

#define AT91C_RTC_ALARM (0x1u << 1) // (RTC) Alarm Flag

#define AT91C_RTC_SECEV (0x1u << 2) // (RTC) Second Event

#define AT91C_RTC_TIMEV (0x1u << 3) // (RTC) Time Event

#define AT91C_RTC_CALEV (0x1u << 4) // (RTC) Calendar event

#define AT91C_RTC_NVTIM (0x1u << 0) // (RTC) Non valid Time

#define AT91C_RTC_NVCAL (0x1u << 1) // (RTC) Non valid Calendar

#define AT91C_RTC_NVTIMALR (0x1u << 2) // (RTC) Non valid time Alarm

#define AT91C_RTC_NVCALALR (0x1u << 3) // (RTC) Nonvalid Calendar Alarm

typedef struct _AT91S_ST {

AT91_REG ST_CR; // Control Register

AT91_REG ST_PIMR; // Period Interval Mode Register

AT91_REG ST_WDMR; // Watchdog Mode Register

AT91_REG ST_RTMR; // Real-time Mode Register

AT91_REG ST_SR; // Status Register

AT91_REG ST_IER; // Interrupt Enable Register

AT91_REG ST_IDR; // Interrupt Disable Register

AT91_REG ST_IMR; // Interrupt Mask Register

AT91_REG ST_RTAR; // Real-time Alarm Register

AT91_REG ST_CRTR; // Current Real-time Register

} AT91S_ST, *AT91PS_ST;

#define AT91C_ST_WDRST (0x1u << 0) // (ST) Watchdog Timer Restart

#define AT91C_ST_PIV (0xFFFFu << 0) // (ST) Watchdog Timer Restart

#define AT91C_ST_WDV (0xFFFFu << 0) // (ST) Watchdog Timer Restart

#define AT91C_ST_RSTEN (0x1u << 16) // (ST) Reset Enable

#define AT91C_ST_EXTEN (0x1u << 17) // (ST) External Signal Assertion Enable

#define AT91C_ST_RTPRES (0xFFFFu << 0) // (ST) Real-time Timer Prescaler Value

#define AT91C_ST_PITS (0x1u << 0) // (ST) Period Interval Timer Interrupt

#define AT91C_ST_WDOVF (0x1u << 1) // (ST) Watchdog Overflow

#define AT91C_ST_RTTINC (0x1u << 2) // (ST) Real-time Timer Increment

#define AT91C_ST_ALMS (0x1u << 3) // (ST) Alarm Status

#define AT91C_ST_ALMV (0xFFFFFu << 0) // (ST) Alarm Value Value

#define AT91C_ST_CRTV (0xFFFFFu << 0) // (ST) Current Real-time Value

typedef struct _AT91S_PMC {

AT91_REG PMC_SCER; // System Clock Enable Register

AT91_REG PMC_SCDR; // System Clock Disable Register

AT91_REG PMC_SCSR; // System Clock Status Register

AT91_REG Reserved0[1]; //

AT91_REG PMC_PCER; // Peripheral Clock Enable Register

AT91_REG PMC_PCDR; // Peripheral Clock Disable Register

AT91_REG PMC_PCSR; // Peripheral Clock Status Register

AT91_REG Reserved1[5]; //

AT91_REG PMC_MCKR; // Master Clock Register

AT91_REG Reserved2[3]; //

AT91_REG PMC_PCKR[8]; // Programmable Clock Register

AT91_REG PMC_IER; // Interrupt Enable Register

AT91_REG PMC_IDR; // Interrupt Disable Register

AT91_REG PMC_SR; // Status Register

AT91_REG PMC_IMR; // Interrupt Mask Register

} AT91S_PMC, *AT91PS_PMC;

#define AT91C_PMC_PCK (0x1u << 0) // (PMC) Processor Clock

#define AT91C_PMC_UDP (0x1u << 1) // (PMC) USB Device Port Clock

#define AT91C_PMC_MCKUDP (0x1u << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend

#define AT91C_PMC_UHP (0x1u << 4) // (PMC) USB Host Port Clock

#define AT91C_PMC_PCK0 (0x1u << 8) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK1 (0x1u << 9) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK2 (0x1u << 10) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK3 (0x1u << 11) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK4 (0x1u << 12) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK5 (0x1u << 13) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK6 (0x1u << 14) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK7 (0x1u << 15) // (PMC) Programmable Clock Output

#define AT91C_PMC_CSS (0x3u << 0) // (PMC) Programmable Clock Selection

#define AT91C_PMC_CSS_SLOW_CLK 0x0u // (PMC) Slow Clock is selected

#define AT91C_PMC_CSS_MAIN_CLK 0x1u // (PMC) Main Clock is selected

#define AT91C_PMC_CSS_PLLA_CLK 0x2u // (PMC) Clock from PLL A is selected

#define AT91C_PMC_CSS_PLLB_CLK 0x3u // (PMC) Clock from PLL B is selected

#define AT91C_PMC_PRES (0x7u << 2) // (PMC) Programmable Clock Prescaler

#define AT91C_PMC_PRES_CLK (0x0u << 2) // (PMC) Selected clock

#define AT91C_PMC_PRES_CLK_2 (0x1u << 2) // (PMC) Selected clock divided by 2

#define AT91C_PMC_PRES_CLK_4 (0x2u << 2) // (PMC) Selected clock divided by 4

#define AT91C_PMC_PRES_CLK_8 (0x3u << 2) // (PMC) Selected clock divided by 8

#define AT91C_PMC_PRES_CLK_16 (0x4u << 2) // (PMC) Selected clock divided by 16

#define AT91C_PMC_PRES_CLK_32 (0x5u << 2) // (PMC) Selected clock divided by 32

#define AT91C_PMC_PRES_CLK_64 (0x6u << 2) // (PMC) Selected clock divided by 64

#define AT91C_PMC_MDIV (0x3u << 8) // (PMC) Master Clock Division

#define AT91C_PMC_MDIV_1 (0x0u << 8) // (PMC) The master clock and the processor clock are the same

#define AT91C_PMC_MDIV_2 (0x1u << 8) // (PMC) The processor clock is twice as fast as the master clock

#define AT91C_PMC_MDIV_3 (0x2u << 8) // (PMC) The processor clock is three times faster than the master clock

#define AT91C_PMC_MDIV_4 (0x3u << 8) // (PMC) The processor clock is four times faster than the master clock

#define AT91C_PMC_MOSCS (0x1u << 0) // (PMC) MOSC Status/Enable/Disable/Mask

#define AT91C_PMC_LOCKA (0x1u << 1) // (PMC) PLL A Status/Enable/Disable/Mask

#define AT91C_PMC_LOCKB (0x1u << 2) // (PMC) PLL B Status/Enable/Disable/Mask

#define AT91C_PMC_MCKRDY (0x1u << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK0RDY (0x1u << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK1RDY (0x1u << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK2RDY (0x1u << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK3RDY (0x1u << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK4RDY (0x1u << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK5RDY (0x1u << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK6RDY (0x1u << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK7RDY (0x1u << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask

typedef struct _AT91S_CKGR {

AT91_REG CKGR_MOR; // Main Oscillator Register

AT91_REG CKGR_MCFR; // Main Clock Frequency Register

AT91_REG CKGR_PLLAR; // PLL A Register

AT91_REG CKGR_PLLBR; // PLL B Register

} AT91S_CKGR, *AT91PS_CKGR;

#define AT91C_CKGR_MOSCEN (0x1u << 0) // (CKGR) Main Oscillator Enable

#define AT91C_CKGR_OSCTEST (0x1u << 1) // (CKGR) Oscillator Test

#define AT91C_CKGR_OSCOUNT (0xFFu << 8) // (CKGR) Main Oscillator Start-up Time

#define AT91C_CKGR_MAINF (0xFFFFu << 0) // (CKGR) Main Clock Frequency

#define AT91C_CKGR_MAINRDY (0x1u << 16) // (CKGR) Main Clock Ready

#define AT91C_CKGR_DIVA (0xFFu << 0) // (CKGR) Divider Selected

#define AT91C_CKGR_DIVA_0 0x0u // (CKGR) Divider output is 0

#define AT91C_CKGR_DIVA_BYPASS 0x1u // (CKGR) Divider is bypassed

#define AT91C_CKGR_PLLACOUNT (0x3Fu << 8) // (CKGR) PLL A Counter

#define AT91C_CKGR_OUTA (0x3u << 14) // (CKGR) PLL A Output Frequency Range

#define AT91C_CKGR_OUTA_0 (0x0u << 14) // (CKGR) Please refer to the PLLA datasheet

#define AT91C_CKGR_OUTA_1 (0x1u << 14) // (CKGR) Please refer to the PLLA datasheet

#define AT91C_CKGR_OUTA_2 (0x2u << 14) // (CKGR) Please refer to the PLLA datasheet

#define AT91C_CKGR_OUTA_3 (0x3u << 14) // (CKGR) Please refer to the PLLA datasheet

#define AT91C_CKGR_MULA (0x7FFu << 16) // (CKGR) PLL A Multiplier

#define AT91C_CKGR_SRCA (0x1u << 29) // (CKGR) PLL A Source

#define AT91C_CKGR_DIVB (0xFFu << 0) // (CKGR) Divider Selected

#define AT91C_CKGR_DIVB_0 0x0u // (CKGR) Divider output is 0

#define AT91C_CKGR_DIVB_BYPASS 0x1u // (CKGR) Divider is bypassed

#define AT91C_CKGR_PLLBCOUNT (0x3Fu << 8) // (CKGR) PLL B Counter

#define AT91C_CKGR_OUTB (0x3u << 14) // (CKGR) PLL B Output Frequency Range

#define AT91C_CKGR_OUTB_0 (0x0u << 14) // (CKGR) Please refer to the PLLB datasheet

#define AT91C_CKGR_OUTB_1 (0x1u << 14) // (CKGR) Please refer to the PLLB datasheet

#define AT91C_CKGR_OUTB_2 (0x2u << 14) // (CKGR) Please refer to the PLLB datasheet

#define AT91C_CKGR_OUTB_3 (0x3u << 14) // (CKGR) Please refer to the PLLB datasheet

#define AT91C_CKGR_MULB (0x7FFu << 16) // (CKGR) PLL B Multiplier

#define AT91C_CKGR_USB_96M (0x1u << 28) // (CKGR) Divider for USB Ports

#define AT91C_CKGR_USB_PLL (0x1u << 29) // (CKGR) PLL Use

typedef struct _AT91S_PIO {

AT91_REG PIO_PER; // PIO Enable Register

AT91_REG PIO_PDR; // PIO Disable Register

AT91_REG PIO_PSR; // PIO Status Register

AT91_REG Reserved0[1]; //

AT91_REG PIO_OER; // Output Enable Register

AT91_REG PIO_ODR; // Output Disable Registerr

AT91_REG PIO_OSR; // Output Status Register

AT91_REG Reserved1[1]; //

AT91_REG PIO_IFER; // Input Filter Enable Register

AT91_REG PIO_IFDR; // Input Filter Disable Register

AT91_REG PIO_IFSR; // Input Filter Status Register

AT91_REG Reserved2[1]; //

AT91_REG PIO_SODR; // Set Output Data Register

AT91_REG PIO_CODR; // Clear Output Data Register

AT91_REG PIO_ODSR; // Output Data Status Register

AT91_REG PIO_PDSR; // Pin Data Status Register

AT91_REG PIO_IER; // Interrupt Enable Register

AT91_REG PIO_IDR; // Interrupt Disable Register

AT91_REG PIO_IMR; // Interrupt Mask Register

AT91_REG PIO_ISR; // Interrupt Status Register

AT91_REG PIO_MDER; // Multi-driver Enable Register

AT91_REG PIO_MDDR; // Multi-driver Disable Register

AT91_REG PIO_MDSR; // Multi-driver Status Register

AT91_REG Reserved3[1]; //

AT91_REG PIO_PPUDR; // Pull-up Disable Register

AT91_REG PIO_PPUER; // Pull-up Enable Register

AT91_REG PIO_PPUSR; // Pad Pull-up Status Register

AT91_REG Reserved4[1]; //

AT91_REG PIO_ASR; // Select A Register

AT91_REG PIO_BSR; // Select B Register

AT91_REG PIO_ABSR; // AB Select Status Register

AT91_REG Reserved5[9]; //

AT91_REG PIO_OWER; // Output Write Enable Register

AT91_REG PIO_OWDR; // Output Write Disable Register

AT91_REG PIO_OWSR; // Output Write Status Register

} AT91S_PIO, *AT91PS_PIO;

typedef struct _AT91S_DBGU {

AT91_REG DBGU_CR; // Control Register

AT91_REG DBGU_MR; // Mode Register

AT91_REG DBGU_IER; // Interrupt Enable Register

AT91_REG DBGU_IDR; // Interrupt Disable Register

AT91_REG DBGU_IMR; // Interrupt Mask Register

AT91_REG DBGU_CSR; // Channel Status Register

AT91_REG DBGU_RHR; // Receiver Holding Register

AT91_REG DBGU_THR; // Transmitter Holding Register

AT91_REG DBGU_BRGR; // Baud Rate Generator Register

AT91_REG Reserved0[7]; //

AT91_REG DBGU_C1R; // Chip ID1 Register

AT91_REG DBGU_C2R; // Chip ID2 Register

AT91_REG DBGU_FNTR; // Force NTRST Register

AT91_REG Reserved1[45]; //

AT91_REG DBGU_RPR; // Receive Pointer Register

AT91_REG DBGU_RCR; // Receive Counter Register

AT91_REG DBGU_TPR; // Transmit Pointer Register

AT91_REG DBGU_TCR; // Transmit Counter Register

AT91_REG DBGU_RNPR; // Receive Next Pointer Register

AT91_REG DBGU_RNCR; // Receive Next Counter Register

AT91_REG DBGU_TNPR; // Transmit Next Pointer Register

AT91_REG DBGU_TNCR; // Transmit Next Counter Register

AT91_REG DBGU_PTCR; // PDC Transfer Control Register

AT91_REG DBGU_PTSR; // PDC Transfer Status Register

} AT91S_DBGU, *AT91PS_DBGU;

#define AT91C_US_RSTRX (0x1u << 2) // (DBGU) Reset Receiver

#define AT91C_US_RSTTX (0x1u << 3) // (DBGU) Reset Transmitter

#define AT91C_US_RXEN (0x1u << 4) // (DBGU) Receiver Enable

#define AT91C_US_RXDIS (0x1u << 5) // (DBGU) Receiver Disable

#define AT91C_US_TXEN (0x1u << 6) // (DBGU) Transmitter Enable

#define AT91C_US_TXDIS (0x1u << 7) // (DBGU) Transmitter Disable

#define AT91C_US_PAR (0x7u << 9) // (DBGU) Parity type

#define AT91C_US_PAR_EVEN (0x0u << 9) // (DBGU) Even Parity

#define AT91C_US_PAR_ODD (0x1u << 9) // (DBGU) Odd Parity

#define AT91C_US_PAR_SPACE (0x2u << 9) // (DBGU) Parity forced to 0 (Space)

#define AT91C_US_PAR_MARK (0x3u << 9) // (DBGU) Parity forced to 1 (Mark)

#define AT91C_US_PAR_NONE (0x4u << 9) // (DBGU) No Parity

#define AT91C_US_PAR_MULTI_DROP (0x6u << 9) // (DBGU) Multi-drop mode

#define AT91C_US_CHMODE (0x3u << 14) // (DBGU) Channel Mode

#define AT91C_US_CHMODE_NORMAL (0x0u << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.

#define AT91C_US_CHMODE_AUTO (0x1u << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.

#define AT91C_US_CHMODE_LOCAL (0x2u << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.

#define AT91C_US_CHMODE_REMOTE (0x3u << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.

#define AT91C_US_RXRDY (0x1u << 0) // (DBGU) RXRDY Interrupt

#define AT91C_US_TXRDY (0x1u << 1) // (DBGU) TXRDY Interrupt

#define AT91C_US_ENDRX (0x1u << 3) // (DBGU) End of Receive Transfer Interrupt

#define AT91C_US_ENDTX (0x1u << 4) // (DBGU) End of Transmit Interrupt

#define AT91C_US_OVRE (0x1u << 5) // (DBGU) Overrun Interrupt

#define AT91C_US_FRAME (0x1u << 6) // (DBGU) Framing Error Interrupt

#define AT91C_US_PARE (0x1u << 7) // (DBGU) Parity Error Interrupt

#define AT91C_US_TXEMPTY (0x1u << 9) // (DBGU) TXEMPTY Interrupt

#define AT91C_US_TXBUFE (0x1u << 11) // (DBGU) TXBUFE Interrupt

#define AT91C_US_RXBUFF (0x1u << 12) // (DBGU) RXBUFF Interrupt

#define AT91C_US_COMM_TX (0x1u << 30) // (DBGU) COMM_TX Interrupt

#define AT91C_US_COMM_RX (0x1u << 31) // (DBGU) COMM_RX Interrupt

#define AT91C_US_FORCE_NTRST (0x1u << 0) // (DBGU) Force NTRST in JTAG

typedef struct _AT91S_PDC {

AT91_REG PDC_RPR; // Receive Pointer Register

AT91_REG PDC_RCR; // Receive Counter Register

AT91_REG PDC_TPR; // Transmit Pointer Register

AT91_REG PDC_TCR; // Transmit Counter Register

AT91_REG PDC_RNPR; // Receive Next Pointer Register

AT91_REG PDC_RNCR; // Receive Next Counter Register

AT91_REG PDC_TNPR; // Transmit Next Pointer Register

AT91_REG PDC_TNCR; // Transmit Next Counter Register

AT91_REG PDC_PTCR; // PDC Transfer Control Register

AT91_REG PDC_PTSR; // PDC Transfer Status Register

} AT91S_PDC, *AT91PS_PDC;

#define AT91C_PDC_RXTEN (0x1u << 0) // (PDC) Receiver Transfer Enable

#define AT91C_PDC_RXTDIS (0x1u << 1) // (PDC) Receiver Transfer Disable

#define AT91C_PDC_TXTEN (0x1u << 8) // (PDC) Transmitter Transfer Enable

#define AT91C_PDC_TXTDIS (0x1u << 9) // (PDC) Transmitter Transfer Disable

typedef struct _AT91S_AIC {

AT91_REG AIC_SMR[32]; // Source Mode Register

AT91_REG AIC_SVR[32]; // Source Vector Register

AT91_REG AIC_IVR; // IRQ Vector Register

AT91_REG AIC_FVR; // FIQ Vector Register

AT91_REG AIC_ISR; // Interrupt Status Register

AT91_REG AIC_IPR; // Interrupt Pending Register

AT91_REG AIC_IMR; // Interrupt Mask Register

AT91_REG AIC_CISR; // Core Interrupt Status Register

AT91_REG Reserved0[2]; //

AT91_REG AIC_IECR; // Interrupt Enable Command Register

AT91_REG AIC_IDCR; // Interrupt Disable Command Register

AT91_REG AIC_ICCR; // Interrupt Clear Command Register

AT91_REG AIC_ISCR; // Interrupt Set Command Register

AT91_REG AIC_EOICR; // End of Interrupt Command Register

AT91_REG AIC_SPU; // Spurious Vector Register

AT91_REG AIC_DCR; // Debug Control Register (Protect)

AT91_REG Reserved1[1]; //

AT91_REG AIC_FFER; // Fast Forcing Enable Register

AT91_REG AIC_FFDR; // Fast Forcing Disable Register

AT91_REG AIC_FFSR; // Fast Forcing Status Register

} AT91S_AIC, *AT91PS_AIC;

#define AT91C_AIC_PRIOR (0x7u << 0) // (AIC) Priority Level

#define AT91C_AIC_PRIOR_LOWEST 0x0u // (AIC) Lowest priority level

#define AT91C_AIC_PRIOR_HIGHEST 0x7u // (AIC) Highest priority level

#define AT91C_AIC_SRCTYPE (0x3u << 5) // (AIC) Interrupt Source Type

#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) // (AIC) Internal Sources Code Label Level Sensitive

#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) // (AIC) Internal Sources Code Label Edge triggered

#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) // (AIC) External Sources Code Label High-level Sensitive

#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) // (AIC) External Sources Code Label Positive Edge triggered

#define AT91C_AIC_NFIQ (0x1u << 0) // (AIC) NFIQ Status

#define AT91C_AIC_NIRQ (0x1u << 1) // (AIC) NIRQ Status

#define AT91C_AIC_DCR_PROT (0x1u << 0) // (AIC) Protection Mode

#define AT91C_AIC_DCR_GMSK (0x1u << 1) // (AIC) General Mask

typedef struct _AT91S_SPI {

AT91_REG SPI_CR; // Control Register

AT91_REG SPI_MR; // Mode Register

AT91_REG SPI_RDR; // Receive Data Register

AT91_REG SPI_TDR; // Transmit Data Register

AT91_REG SPI_SR; // Status Register

AT91_REG SPI_IER; // Interrupt Enable Register

AT91_REG SPI_IDR; // Interrupt Disable Register

AT91_REG SPI_IMR; // Interrupt Mask Register

AT91_REG Reserved0[4]; //

AT91_REG SPI_CSR[4]; // Chip Select Register

AT91_REG Reserved1[48]; //

AT91_REG SPI_RPR; // Receive Pointer Register

AT91_REG SPI_RCR; // Receive Counter Register

AT91_REG SPI_TPR; // Transmit Pointer Register

AT91_REG SPI_TCR; // Transmit Counter Register

AT91_REG SPI_RNPR; // Receive Next Pointer Register

AT91_REG SPI_RNCR; // Receive Next Counter Register

AT91_REG SPI_TNPR; // Transmit Next Pointer Register

AT91_REG SPI_TNCR; // Transmit Next Counter Register

AT91_REG SPI_PTCR; // PDC Transfer Control Register

AT91_REG SPI_PTSR; // PDC Transfer Status Register

} AT91S_SPI, *AT91PS_SPI;

#define AT91C_SPI_SPIEN (0x1u << 0) // (SPI) SPI Enable

#define AT91C_SPI_SPIDIS (0x1u << 1) // (SPI) SPI Disable

#define AT91C_SPI_SWRST (0x1u << 7) // (SPI) SPI Software reset

#define AT91C_SPI_MSTR (0x1u << 0) // (SPI) Master/Slave Mode

#define AT91C_SPI_PS (0x1u << 1) // (SPI) Peripheral Select

#define AT91C_SPI_PS_FIXED (0x0u << 1) // (SPI) Fixed Peripheral Select

#define AT91C_SPI_PS_VARIABLE (0x1u << 1) // (SPI) Variable Peripheral Select

#define AT91C_SPI_PCSDEC (0x1u << 2) // (SPI) Chip Select Decode

#define AT91C_SPI_DIV32 (0x1u << 3) // (SPI) Clock Selection

#define AT91C_SPI_MODFDIS (0x1u << 4) // (SPI) Mode Fault Detection

#define AT91C_SPI_LLB (0x1u << 7) // (SPI) Clock Selection

#define AT91C_SPI_PCS (0xFu << 16) // (SPI) Peripheral Chip Select

#define AT91C_SPI_DLYBCS (0xFFu << 24) // (SPI) Delay Between Chip Selects

#define AT91C_SPI_RD (0xFFFFu << 0) // (SPI) Receive Data

#define AT91C_SPI_RPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status

#define AT91C_SPI_TD (0xFFFFu << 0) // (SPI) Transmit Data

#define AT91C_SPI_TPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status

#define AT91C_SPI_RDRF (0x1u << 0) // (SPI) Receive Data Register Full

#define AT91C_SPI_TDRE (0x1u << 1) // (SPI) Transmit Data Register Empty

#define AT91C_SPI_MODF (0x1u << 2) // (SPI) Mode Fault Error

#define AT91C_SPI_OVRES (0x1u << 3) // (SPI) Overrun Error Status

#define AT91C_SPI_SPENDRX (0x1u << 4) // (SPI) End of Receiver Transfer

#define AT91C_SPI_SPENDTX (0x1u << 5) // (SPI) End of Receiver Transfer

#define AT91C_SPI_RXBUFF (0x1u << 6) // (SPI) RXBUFF Interrupt

#define AT91C_SPI_TXBUFE (0x1u << 7) // (SPI) TXBUFE Interrupt

#define AT91C_SPI_SPIENS (0x1u << 16) // (SPI) Enable Status

#define AT91C_SPI_CPOL (0x1u << 0) // (SPI) Clock Polarity

#define AT91C_SPI_NCPHA (0x1u << 1) // (SPI) Clock Phase

#define AT91C_SPI_BITS (0xFu << 4) // (SPI) Bits Per Transfer

#define AT91C_SPI_BITS_8 (0x0u << 4) // (SPI) 8 Bits Per transfer

#define AT91C_SPI_BITS_9 (0x1u << 4) // (SPI) 9 Bits Per transfer

#define AT91C_SPI_BITS_10 (0x2u << 4) // (SPI) 10 Bits Per transfer

#define AT91C_SPI_BITS_11 (0x3u << 4) // (SPI) 11 Bits Per transfer

#define AT91C_SPI_BITS_12 (0x4u << 4) // (SPI) 12 Bits Per transfer

#define AT91C_SPI_BITS_13 (0x5u << 4) // (SPI) 13 Bits Per transfer

#define AT91C_SPI_BITS_14 (0x6u << 4) // (SPI) 14 Bits Per transfer

#define AT91C_SPI_BITS_15 (0x7u << 4) // (SPI) 15 Bits Per transfer

#define AT91C_SPI_BITS_16 (0x8u << 4) // (SPI) 16 Bits Per transfer

#define AT91C_SPI_SCBR (0xFFu << 8) // (SPI) Serial Clock Baud Rate

#define AT91C_SPI_DLYBS (0xFFu << 16) // (SPI) Serial Clock Baud Rate

#define AT91C_SPI_DLYBCT (0xFFu << 24) // (SPI) Delay Between Consecutive Transfers

typedef struct _AT91S_SSC {

AT91_REG SSC_CR; // Control Register

AT91_REG SSC_CMR; // Clock Mode Register

AT91_REG Reserved0[2]; //

AT91_REG SSC_RCMR; // Receive Clock ModeRegister

AT91_REG SSC_RFMR; // Receive Frame Mode Register

AT91_REG SSC_TCMR; // Transmit Clock Mode Register

AT91_REG SSC_TFMR; // Transmit Frame Mode Register

AT91_REG SSC_RHR; // Receive Holding Register

AT91_REG SSC_THR; // Transmit Holding Register

AT91_REG Reserved1[2]; //

AT91_REG SSC_RSHR; // Receive Sync Holding Register

AT91_REG SSC_TSHR; // Transmit Sync Holding Register

AT91_REG SSC_RC0R; // Receive Compare 0 Register

AT91_REG SSC_RC1R; // Receive Compare 1 Register

AT91_REG SSC_SR; // Status Register

AT91_REG SSC_IER; // Interrupt Enable Register

AT91_REG SSC_IDR; // Interrupt Disable Register

AT91_REG SSC_IMR; // Interrupt Mask Register

AT91_REG Reserved2[44]; //

AT91_REG SSC_RPR; // Receive Pointer Register

AT91_REG SSC_RCR; // Receive Counter Register

AT91_REG SSC_TPR; // Transmit Pointer Register

AT91_REG SSC_TCR; // Transmit Counter Register

AT91_REG SSC_RNPR; // Receive Next Pointer Register

AT91_REG SSC_RNCR; // Receive Next Counter Register

AT91_REG SSC_TNPR; // Transmit Next Pointer Register

AT91_REG SSC_TNCR; // Transmit Next Counter Register

AT91_REG SSC_PTCR; // PDC Transfer Control Register

AT91_REG SSC_PTSR; // PDC Transfer Status Register

} AT91S_SSC, *AT91PS_SSC;

#define AT91C_SSC_RXEN (0x1u << 0) // (SSC) Receive Enable

#define AT91C_SSC_RXDIS (0x1u << 1) // (SSC) Receive Disable

#define AT91C_SSC_TXEN (0x1u << 8) // (SSC) Transmit Enable

#define AT91C_SSC_TXDIS (0x1u << 9) // (SSC) Transmit Disable

#define AT91C_SSC_SWRST (0x1u << 15) // (SSC) Software Reset

#define AT91C_SSC_CKS (0x3u << 0) // (SSC) Receive/Transmit Clock Selection

#define AT91C_SSC_CKS_DIV 0x0u // (SSC) Divided Clock

#define AT91C_SSC_CKS_TK 0x1u // (SSC) TK Clock signal

#define AT91C_SSC_CKS_RK 0x2u // (SSC) RK pin

#define AT91C_SSC_CKO (0x7u << 2) // (SSC) Receive/Transmit Clock Output Mode Selection

#define AT91C_SSC_CKO_NONE (0x0u << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only

#define AT91C_SSC_CKO_CONTINOUS (0x1u << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output

#define AT91C_SSC_CKO_DATA_TX (0x2u << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output

#define AT91C_SSC_CKI (0x1u << 5) // (SSC) Receive/Transmit Clock Inversion

#define AT91C_SSC_CKG (0x3u << 6) // (SSC) Receive/Transmit Clock Gating Selection

#define AT91C_SSC_CKG_NONE (0x0u << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock

#define AT91C_SSC_CKG_LOW (0x1u << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low

#define AT91C_SSC_CKG_HIGH (0x2u << 6) // (SSC) Receive/Transmit Clock enabled only if RF High

#define AT91C_SSC_START (0xFu << 8) // (SSC) Receive/Transmit Start Selection

#define AT91C_SSC_START_CONTINOUS (0x0u << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.

#define AT91C_SSC_START_TX (0x1u << 8) // (SSC) Transmit/Receive start

#define AT91C_SSC_START_LOW_RF (0x2u << 8) // (SSC) Detection of a low level on RF input

#define AT91C_SSC_START_HIGH_RF (0x3u << 8) // (SSC) Detection of a high level on RF input

#define AT91C_SSC_START_FALL_RF (0x4u << 8) // (SSC) Detection of a falling edge on RF input

#define AT91C_SSC_START_RISE_RF (0x5u << 8) // (SSC) Detection of a rising edge on RF input

#define AT91C_SSC_START_LEVEL_RF (0x6u << 8) // (SSC) Detection of any level change on RF input

#define AT91C_SSC_START_EDGE_RF (0x7u << 8) // (SSC) Detection of any edge on RF input

#define AT91C_SSC_START_0 (0x8u << 8) // (SSC) Compare 0

#define AT91C_SSC_STOP (0x1u << 12) // (SSC) Receive Stop Selection

#define AT91C_SSC_STTOUT (0x1u << 15) // (SSC) Receive/Transmit Start Output Selection

#define AT91C_SSC_STTDLY (0xFFu << 16) // (SSC) Receive/Transmit Start Delay

#define AT91C_SSC_PERIOD (0xFFu << 24) // (SSC) Receive/Transmit Period Divider Selection

#define AT91C_SSC_DATLEN (0x1Fu << 0) // (SSC) Data Length

#define AT91C_SSC_LOOP (0x1u << 5) // (SSC) Loop Mode

#define AT91C_SSC_MSBF (0x1u << 7) // (SSC) Most Significant Bit First

#define AT91C_SSC_DATNB (0xFu << 8) // (SSC) Data Number per Frame

#define AT91C_SSC_FSLEN (0xFu << 16) // (SSC) Receive/Transmit Frame Sync length

#define AT91C_SSC_FSOS (0x7u << 20) // (SSC) Receive/Transmit Frame Sync Output Selection

#define AT91C_SSC_FSOS_NONE (0x0u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only

#define AT91C_SSC_FSOS_NEGATIVE (0x1u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse

#define AT91C_SSC_FSOS_POSITIVE (0x2u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse

#define AT91C_SSC_FSOS_LOW (0x3u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer

#define AT91C_SSC_FSOS_HIGH (0x4u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer

#define AT91C_SSC_FSOS_TOGGLE (0x5u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer

#define AT91C_SSC_FSEDGE (0x1u << 24) // (SSC) Frame Sync Edge Detection

#define AT91C_SSC_DATDEF (0x1u << 5) // (SSC) Data Default Value

#define AT91C_SSC_FSDEN (0x1u << 23) // (SSC) Frame Sync Data Enable

#define AT91C_SSC_TXRDY (0x1u << 0) // (SSC) Transmit Ready

#define AT91C_SSC_TXEMPTY (0x1u << 1) // (SSC) Transmit Empty

#define AT91C_SSC_ENDTX (0x1u << 2) // (SSC) End Of Transmission

#define AT91C_SSC_TXBUFE (0x1u << 3) // (SSC) Transmit Buffer Empty

#define AT91C_SSC_RXRDY (0x1u << 4) // (SSC) Receive Ready

#define AT91C_SSC_OVRUN (0x1u << 5) // (SSC) Receive Overrun

#define AT91C_SSC_ENDRX (0x1u << 6) // (SSC) End of Reception

#define AT91C_SSC_RXBUFF (0x1u << 7) // (SSC) Receive Buffer Full

#define AT91C_SSC_CP0 (0x1u << 8) // (SSC) Compare 0

#define AT91C_SSC_CP1 (0x1u << 9) // (SSC) Compare 1

#define AT91C_SSC_TXSYN (0x1u << 10) // (SSC) Transmit Sync

#define AT91C_SSC_RXSYN (0x1u << 11) // (SSC) Receive Sync

#define AT91C_SSC_TXENA (0x1u << 16) // (SSC) Transmit Enable

#define AT91C_SSC_RXENA (0x1u << 17) // (SSC) Receive Enable

typedef struct _AT91S_USART {

AT91_REG US_CR; // Control Register

AT91_REG US_MR; // Mode Register

AT91_REG US_IER; // Interrupt Enable Register

AT91_REG US_IDR; // Interrupt Disable Register

AT91_REG US_IMR; // Interrupt Mask Register

AT91_REG US_CSR; // Channel Status Register

AT91_REG US_RHR; // Receiver Holding Register

AT91_REG US_THR; // Transmitter Holding Register

AT91_REG US_BRGR; // Baud Rate Generator Register

AT91_REG US_RTOR; // Receiver Time-out Register

AT91_REG US_TTGR; // Transmitter Time-guard Register

AT91_REG Reserved0[5]; //

AT91_REG US_FIDI; // FI_DI_Ratio Register

AT91_REG US_NER; // Nb Errors Register

AT91_REG US_XXR; // XON_XOFF Register

AT91_REG US_IF; // IRDA_FILTER Register

AT91_REG Reserved1[44]; //

AT91_REG US_RPR; // Receive Pointer Register

AT91_REG US_RCR; // Receive Counter Register

AT91_REG US_TPR; // Transmit Pointer Register

AT91_REG US_TCR; // Transmit Counter Register

AT91_REG US_RNPR; // Receive Next Pointer Register

AT91_REG US_RNCR; // Receive Next Counter Register

AT91_REG US_TNPR; // Transmit Next Pointer Register

AT91_REG US_TNCR; // Transmit Next Counter Register

AT91_REG US_PTCR; // PDC Transfer Control Register

AT91_REG US_PTSR; // PDC Transfer Status Register

} AT91S_USART, *AT91PS_USART;

#define AT91C_US_RSTSTA (0x1u << 8) // (USART) Reset Status Bits

#define AT91C_US_STTBRK (0x1u << 9) // (USART) Start Break

#define AT91C_US_STPBRK (0x1u << 10) // (USART) Stop Break

#define AT91C_US_STTTO (0x1u << 11) // (USART) Start Time-out

#define AT91C_US_SENDA (0x1u << 12) // (USART) Send Address

#define AT91C_US_RSTIT (0x1u << 13) // (USART) Reset Iterations

#define AT91C_US_RSTNACK (0x1u << 14) // (USART) Reset Non Acknowledge

#define AT91C_US_RETTO (0x1u << 15) // (USART) Rearm Time-out

#define AT91C_US_DTREN (0x1u << 16) // (USART) Data Terminal ready Enable

#define AT91C_US_DTRDIS (0x1u << 17) // (USART) Data Terminal ready Disable

#define AT91C_US_RTSEN (0x1u << 18) // (USART) Request to Send enable

#define AT91C_US_RTSDIS (0x1u << 19) // (USART) Request to Send Disable

#define AT91C_US_USMODE (0xFu << 0) // (USART) Usart mode

#define AT91C_US_USMODE_NORMAL 0x0u // (USART) Normal

#define AT91C_US_USMODE_RS485 0x1u // (USART) RS485

#define AT91C_US_USMODE_HWHSH 0x2u // (USART) Hardware Handshaking

#define AT91C_US_USMODE_MODEM 0x3u // (USART) Modem

#define AT91C_US_USMODE_ISO7816_0 0x4u // (USART) ISO7816 protocol: T = 0

#define AT91C_US_USMODE_ISO7816_1 0x6u // (USART) ISO7816 protocol: T = 1

#define AT91C_US_USMODE_IRDA 0x8u // (USART) IrDA

#define AT91C_US_USMODE_SWHSH 0xCu // (USART) Software Handshaking

#define AT91C_US_CLKS (0x3u << 4) // (USART) Clock Selection (Baud Rate generator Input Clock

#define AT91C_US_CLKS_CLOCK (0x0u << 4) // (USART) Clock

#define AT91C_US_CLKS_FDIV1 (0x1u << 4) // (USART) fdiv1

#define AT91C_US_CLKS_SLOW (0x2u << 4) // (USART) slow_clock (ARM)

#define AT91C_US_CLKS_EXT (0x3u << 4) // (USART) External (SCK)

#define AT91C_US_CHRL (0x3u << 6) // (USART) Clock Selection (Baud Rate generator Input Clock

#define AT91C_US_CHRL_5_BITS (0x0u << 6) // (USART) Character Length: 5 bits

#define AT91C_US_CHRL_6_BITS (0x1u << 6) // (USART) Character Length: 6 bits

#define AT91C_US_CHRL_7_BITS (0x2u << 6) // (USART) Character Length: 7 bits

#define AT91C_US_CHRL_8_BITS (0x3u << 6) // (USART) Character Length: 8 bits

#define AT91C_US_SYNC (0x1u << 8) // (USART) Synchronous Mode Select

#define AT91C_US_NBSTOP (0x3u << 12) // (USART) Number of Stop bits

#define AT91C_US_NBSTOP_1_BIT (0x0u << 12) // (USART) 1 stop bit

#define AT91C_US_NBSTOP_15_BIT (0x1u << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits

#define AT91C_US_NBSTOP_2_BIT (0x2u << 12) // (USART) 2 stop bits

#define AT91C_US_MSBF (0x1u << 16) // (USART) Bit Order

#define AT91C_US_MODE9 (0x1u << 17) // (USART) 9-bit Character length

#define AT91C_US_CKLO (0x1u << 18) // (USART) Clock Output Select

#define AT91C_US_OVER (0x1u << 19) // (USART) Over Sampling Mode

#define AT91C_US_INACK (0x1u << 20) // (USART) Inhibit Non Acknowledge

#define AT91C_US_DSNACK (0x1u << 21) // (USART) Disable Successive NACK

#define AT91C_US_MAX_ITER (0x1u << 24) // (USART) Number of Repetitions

#define AT91C_US_FILTER (0x1u << 28) // (USART) Receive Line Filter

#define AT91C_US_RXBRK (0x1u << 2) // (USART) Break Received/End of Break

#define AT91C_US_TIMEOUT (0x1u << 8) // (USART) Receiver Time-out

#define AT91C_US_ITERATION (0x1u << 10) // (USART) Max number of Repetitions Reached

#define AT91C_US_NACK (0x1u << 13) // (USART) Non Acknowledge

#define AT91C_US_RIIC (0x1u << 16) // (USART) Ring INdicator Input Change Flag

#define AT91C_US_DSRIC (0x1u << 17) // (USART) Data Set Ready Input Change Flag

#define AT91C_US_DCDIC (0x1u << 18) // (USART) Data Carrier Flag

#define AT91C_US_CTSIC (0x1u << 19) // (USART) Clear To Send Input Change Flag

#define AT91C_US_RI (0x1u << 20) // (USART) Image of RI Input

#define AT91C_US_DSR (0x1u << 21) // (USART) Image of DSR Input

#define AT91C_US_DCD (0x1u << 22) // (USART) Image of DCD Input

#define AT91C_US_CTS (0x1u << 23) // (USART) Image of CTS Input

typedef struct _AT91S_TWI {

AT91_REG TWI_CR; // Control Register

AT91_REG TWI_MMR; // Master Mode Register

AT91_REG TWI_SMR; // Slave Mode Register

AT91_REG TWI_IADR; // Internal Address Register

AT91_REG TWI_CWGR; // Clock Waveform Generator Register

AT91_REG Reserved0[3]; //

AT91_REG TWI_SR; // Status Register

AT91_REG TWI_IER; // Interrupt Enable Register

AT91_REG TWI_IDR; // Interrupt Disable Register

AT91_REG TWI_IMR; // Interrupt Mask Register

AT91_REG TWI_RHR; // Receive Holding Register

AT91_REG TWI_THR; // Transmit Holding Register

} AT91S_TWI, *AT91PS_TWI;

#define AT91C_TWI_START (0x1u << 0) // (TWI) Send a START Condition

#define AT91C_TWI_STOP (0x1u << 1) // (TWI) Send a STOP Condition

#define AT91C_TWI_MSEN (0x1u << 2) // (TWI) TWI Master Transfer Enabled

#define AT91C_TWI_MSDIS (0x1u << 3) // (TWI) TWI Master Transfer Disabled

#define AT91C_TWI_SVEN (0x1u << 4) // (TWI) TWI Slave Transfer Enabled

#define AT91C_TWI_SVDIS (0x1u << 5) // (TWI) TWI Slave Transfer Disabled

#define AT91C_TWI_SWRST (0x1u << 7) // (TWI) Software Reset

#define AT91C_TWI_IADRSZ (0x3u << 8) // (TWI) Internal Device Address Size

#define AT91C_TWI_IADRSZ_NO (0x0u << 8) // (TWI) No internal device address

#define AT91C_TWI_IADRSZ_1_BYTE (0x1u << 8) // (TWI) One-byte internal device address

#define AT91C_TWI_IADRSZ_2_BYTE (0x2u << 8) // (TWI) Two-byte internal device address

#define AT91C_TWI_IADRSZ_3_BYTE (0x3u << 8) // (TWI) Three-byte internal device address

#define AT91C_TWI_MREAD (0x1u << 12) // (TWI) Master Read Direction

#define AT91C_TWI_DADR (0x7Fu << 16) // (TWI) Device Address

#define AT91C_TWI_SADR (0x7Fu << 16) // (TWI) Slave Device Address

#define AT91C_TWI_CLDIV (0xFFu << 0) // (TWI) Clock Low Divider

#define AT91C_TWI_CHDIV (0xFFu << 8) // (TWI) Clock High Divider

#define AT91C_TWI_CKDIV (0x7u << 16) // (TWI) Clock Divider

#define AT91C_TWI_TXCOMP (0x1u << 0) // (TWI) Transmission Completed

#define AT91C_TWI_RXRDY (0x1u << 1) // (TWI) Receive holding register ReaDY

#define AT91C_TWI_TXRDY (0x1u << 2) // (TWI) Transmit holding register ReaDY

#define AT91C_TWI_SVREAD (0x1u << 3) // (TWI) Slave Read

#define AT91C_TWI_SVACC (0x1u << 4) // (TWI) Slave Access

#define AT91C_TWI_GCACC (0x1u << 5) // (TWI) General Call Access

#define AT91C_TWI_OVRE (0x1u << 6) // (TWI) Overrun Error

#define AT91C_TWI_UNRE (0x1u << 7) // (TWI) Underrun Error

#define AT91C_TWI_NACK (0x1u << 8) // (TWI) Not Acknowledged

#define AT91C_TWI_ARBLST (0x1u << 9) // (TWI) Arbitration Lost

typedef struct _AT91S_MCI {

AT91_REG MCI_CR; // MCI Control Register

AT91_REG MCI_MR; // MCI Mode Register

AT91_REG MCI_DTOR; // MCI Data Timeout Register

AT91_REG MCI_SDCR; // MCI SD Card Register

AT91_REG MCI_ARGR; // MCI Argument Register

AT91_REG MCI_CMDR; // MCI Command Register

AT91_REG Reserved0[2]; //

AT91_REG MCI_RSPR[4]; // MCI Response Register

AT91_REG MCI_RDR; // MCI Receive Data Register

AT91_REG MCI_TDR; // MCI Transmit Data Register

AT91_REG Reserved1[2]; //

AT91_REG MCI_SR; // MCI Status Register

AT91_REG MCI_IER; // MCI Interrupt Enable Register

AT91_REG MCI_IDR; // MCI Interrupt Disable Register

AT91_REG MCI_IMR; // MCI Interrupt Mask Register

AT91_REG Reserved2[44]; //

AT91_REG MCI_RPR; // Receive Pointer Register

AT91_REG MCI_RCR; // Receive Counter Register

AT91_REG MCI_TPR; // Transmit Pointer Register

AT91_REG MCI_TCR; // Transmit Counter Register

AT91_REG MCI_RNPR; // Receive Next Pointer Register

AT91_REG MCI_RNCR; // Receive Next Counter Register

AT91_REG MCI_TNPR; // Transmit Next Pointer Register

AT91_REG MCI_TNCR; // Transmit Next Counter Register

AT91_REG MCI_PTCR; // PDC Transfer Control Register

AT91_REG MCI_PTSR; // PDC Transfer Status Register

} AT91S_MCI, *AT91PS_MCI;

#define AT91C_MCI_MCIEN (0x1u << 0) // (MCI) Multimedia Interface Enable

#define AT91C_MCI_MCIDIS (0x1u << 1) // (MCI) Multimedia Interface Disable

#define AT91C_MCI_PWSEN (0x1u << 2) // (MCI) Power Save Mode Enable

#define AT91C_MCI_PWSDIS (0x1u << 3) // (MCI) Power Save Mode Disable

#define AT91C_MCI_CLKDIV (0x1u << 0) // (MCI) Clock Divider

#define AT91C_MCI_PWSDIV (0x1u << 8) // (MCI) Power Saving Divider

#define AT91C_MCI_PDCPADV (0x1u << 14) // (MCI) PDC Padding Value

#define AT91C_MCI_PDCMODE (0x1u << 15) // (MCI) PDC Oriented Mode

#define AT91C_MCI_BLKLEN (0x1u << 18) // (MCI) Data Block Length

#define AT91C_MCI_DTOCYC (0x1u << 0) // (MCI) Data Timeout Cycle Number

#define AT91C_MCI_DTOMUL (0x7u << 4) // (MCI) Data Timeout Multiplier

#define AT91C_MCI_DTOMUL_1 (0x0u << 4) // (MCI) DTOCYC x 1

#define AT91C_MCI_DTOMUL_16 (0x1u << 4) // (MCI) DTOCYC x 16

#define AT91C_MCI_DTOMUL_128 (0x2u << 4) // (MCI) DTOCYC x 128

#define AT91C_MCI_DTOMUL_256 (0x3u << 4) // (MCI) DTOCYC x 256

#define AT91C_MCI_DTOMUL_1024 (0x4u << 4) // (MCI) DTOCYC x 1024

#define AT91C_MCI_DTOMUL_4096 (0x5u << 4) // (MCI) DTOCYC x 4096

#define AT91C_MCI_DTOMUL_65536 (0x6u << 4) // (MCI) DTOCYC x 65536

#define AT91C_MCI_DTOMUL_1048576 (0x7u << 4) // (MCI) DTOCYC x 1048576

#define AT91C_MCI_SCDSEL (0x1u << 0) // (MCI) SD Card Selector

#define AT91C_MCI_SCDBUS (0x1u << 7) // (MCI) SD Card Bus Width

#define AT91C_MCI_CMDRDY (0x1u << 0) // (MCI) Command Ready flag

#define AT91C_MCI_RXRDY (0x1u << 1) // (MCI) RX Ready flag

#define AT91C_MCI_TXRDY (0x1u << 2) // (MCI) TX Ready flag

#define AT91C_MCI_BLKE (0x1u << 3) // (MCI) Data Block Transfer Ended flag

#define AT91C_MCI_DTIP (0x1u << 4) // (MCI) Data Transfer in Progress flag

#define AT91C_MCI_NOTBUSY (0x1u << 5) // (MCI) Data Line Not Busy flag

#define AT91C_MCI_ENDRX (0x1u << 6) // (MCI) End of RX Buffer flag

#define AT91C_MCI_ENDTX (0x1u << 7) // (MCI) End of TX Buffer flag

#define AT91C_MCI_RXBUFF (0x1u << 14) // (MCI) RX Buffer Full flag

#define AT91C_MCI_TXBUFE (0x1u << 15) // (MCI) TX Buffer Empty flag

#define AT91C_MCI_RINDE (0x1u << 16) // (MCI) Response Index Error flag

#define AT91C_MCI_RDIRE (0x1u << 17) // (MCI) Response Direction Error flag

#define AT91C_MCI_RCRCE (0x1u << 18) // (MCI) Response CRC Error flag

#define AT91C_MCI_RENDE (0x1u << 19) // (MCI) Response End Bit Error flag

#define AT91C_MCI_RTOE (0x1u << 20) // (MCI) Response Time-out Error flag

#define AT91C_MCI_DCRCE (0x1u << 21) // (MCI) data CRC Error flag

#define AT91C_MCI_DTOE (0x1u << 22) // (MCI) Data timeout Error flag

#define AT91C_MCI_OVRE (0x1u << 30) // (MCI) Overrun flag

#define AT91C_MCI_UNRE (0x1u << 31) // (MCI) Underrun flag

typedef struct _AT91S_UDP {

AT91_REG UDP_NUM; // Frame Number Register

AT91_REG UDP_GLBSTATE; // Global State Register

AT91_REG UDP_FADDR; // Function Address Register

AT91_REG Reserved0[1]; //

AT91_REG UDP_IER; // Interrupt Enable Register

AT91_REG UDP_IDR; // Interrupt Disable Register

AT91_REG UDP_IMR; // Interrupt Mask Register

AT91_REG UDP_ISR; // Interrupt Status Register

AT91_REG UDP_ICR; // Interrupt Clear Register

AT91_REG Reserved1[1]; //

AT91_REG UDP_RSTEP; // Reset Endpoint Register

AT91_REG Reserved2[1]; //

AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register

AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register

} AT91S_UDP, *AT91PS_UDP;

#define AT91C_UDP_FRM_NUM (0x7FFu << 0) // (UDP) Frame Number as Defined in the Packet Field Formats

#define AT91C_UDP_FRM_ERR (0x1u << 16) // (UDP) Frame Error

#define AT91C_UDP_FRM_OK (0x1u << 17) // (UDP) Frame OK

#define AT91C_UDP_FADDEN (0x1u << 0) // (UDP) Function Address Enable

#define AT91C_UDP_CONFG (0x1u << 1) // (UDP) Configured

#define AT91C_UDP_RMWUPE (0x1u << 2) // (UDP) Remote Wake Up Enable

#define AT91C_UDP_RSMINPR (0x1u << 3) // (UDP) A Resume Has Been Sent to the Host

#define AT91C_UDP_FADD (0xFFu << 0) // (UDP) Function Address Value

#define AT91C_UDP_FEN (0x1u << 8) // (UDP) Function Enable

#define AT91C_UDP_EPINT0 (0x1u << 0) // (UDP) Endpoint 0 Interrupt

#define AT91C_UDP_EPINT1 (0x1u << 1) // (UDP) Endpoint 0 Interrupt

#define AT91C_UDP_EPINT2 (0x1u << 2) // (UDP) Endpoint 2 Interrupt

#define AT91C_UDP_EPINT3 (0x1u << 3) // (UDP) Endpoint 3 Interrupt

#define AT91C_UDP_EPINT4 (0x1u << 4) // (UDP) Endpoint 4 Interrupt

#define AT91C_UDP_EPINT5 (0x1u << 5) // (UDP) Endpoint 5 Interrupt

#define AT91C_UDP_EPINT6 (0x1u << 6) // (UDP) Endpoint 6 Interrupt

#define AT91C_UDP_EPINT7 (0x1u << 7) // (UDP) Endpoint 7 Interrupt

#define AT91C_UDP_RXSUSP (0x1u << 8) // (UDP) USB Suspend Interrupt

#define AT91C_UDP_RXRSM (0x1u << 9) // (UDP) USB Resume Interrupt

#define AT91C_UDP_EXTRSM (0x1u << 10) // (UDP) USB External Resume Interrupt

#define AT91C_UDP_SOFINT (0x1u << 11) // (UDP) USB Start Of frame Interrupt

#define AT91C_UDP_WAKEUP (0x1u << 13) // (UDP) USB Resume Interrupt

#define AT91C_UDP_ENDBUSRES (0x1u << 12) // (UDP) USB End Of Bus Reset Interrupt

#define AT91C_UDP_EP0 (0x1u << 0) // (UDP) Reset Endpoint 0

#define AT91C_UDP_EP1 (0x1u << 1) // (UDP) Reset Endpoint 1

#define AT91C_UDP_EP2 (0x1u << 2) // (UDP) Reset Endpoint 2

#define AT91C_UDP_EP3 (0x1u << 3) // (UDP) Reset Endpoint 3

#define AT91C_UDP_EP4 (0x1u << 4) // (UDP) Reset Endpoint 4

#define AT91C_UDP_EP5 (0x1u << 5) // (UDP) Reset Endpoint 5

#define AT91C_UDP_EP6 (0x1u << 6) // (UDP) Reset Endpoint 6

#define AT91C_UDP_EP7 (0x1u << 7) // (UDP) Reset Endpoint 7

#define AT91C_UDP_TXCOMP (0x1u << 0) // (UDP) Generates an IN packet with data previously written in the DPR

#define AT91C_UDP_RX_DATA_BK0 (0x1u << 1) // (UDP) Receive Data Bank 0

#define AT91C_UDP_RXSETUP (0x1u << 2) // (UDP) Sends STALL to the Host (Control endpoints)

#define AT91C_UDP_ISOERROR (0x1u << 3) // (UDP) Isochronous error (Isochronous endpoints)

#define AT91C_UDP_TXPKTRDY (0x1u << 4) // (UDP) Transmit Packet Ready

#define AT91C_UDP_FORCESTALL (0x1u << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).

#define AT91C_UDP_RX_DATA_BK1 (0x1u << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).

#define AT91C_UDP_DIR (0x1u << 7) // (UDP) Transfer Direction

#define AT91C_UDP_EPTYPE (0x7u << 8) // (UDP) Endpoint type

#define AT91C_UDP_EPTYPE_CTRL (0x0u << 8) // (UDP) Control

#define AT91C_UDP_EPTYPE_ISO_OUT (0x1u << 8) // (UDP) Isochronous OUT

#define AT91C_UDP_EPTYPE_BULK_OUT (0x2u << 8) // (UDP) Bulk OUT

#define AT91C_UDP_EPTYPE_INT_OUT (0x3u << 8) // (UDP) Interrupt OUT

#define AT91C_UDP_EPTYPE_ISO_IN (0x5u << 8) // (UDP) Isochronous IN

#define AT91C_UDP_EPTYPE_BULK_IN (0x6u << 8) // (UDP) Bulk IN

#define AT91C_UDP_EPTYPE_INT_IN (0x7u << 8) // (UDP) Interrupt IN

#define AT91C_UDP_DTGLE (0x1u << 11) // (UDP) Data Toggle

#define AT91C_UDP_EPEDS (0x1u << 15) // (UDP) Endpoint Enable Disable

#define AT91C_UDP_RXBYTECNT (0x7FFu << 16) // (UDP) Number Of Bytes Available in the FIFO

typedef struct _AT91S_TC {

AT91_REG TC_CCR; // Channel Control Register

AT91_REG TC_CMR; // Channel Mode Register

AT91_REG Reserved0[2]; //

AT91_REG TC_CV; // Counter Value

AT91_REG TC_RA; // Register A

AT91_REG TC_RB; // Register B

AT91_REG TC_RC; // Register C

AT91_REG TC_SR; // Status Register

AT91_REG TC_IER; // Interrupt Enable Register

AT91_REG TC_IDR; // Interrupt Disable Register

AT91_REG TC_IMR; // Interrupt Mask Register

} AT91S_TC, *AT91PS_TC;

#define AT91C_TC_CLKEN (0x1u << 0) // (TC) Counter Clock Enable Command

#define AT91C_TC_CLKDIS (0x1u << 1) // (TC) Counter Clock Disable Command

#define AT91C_TC_SWTRG (0x1u << 2) // (TC) Software Trigger Command

#define AT91C_TC_CPCSTOP (0x1u << 6) // (TC) Counter Clock Stopped with RC Compare

#define AT91C_TC_CPCDIS (0x1u << 7) // (TC) Counter Clock Disable with RC Compare

#define AT91C_TC_EEVTEDG (0x3u << 8) // (TC) External Event Edge Selection

#define AT91C_TC_EEVTEDG_NONE (0x0u << 8) // (TC) Edge: None

#define AT91C_TC_EEVTEDG_RISING (0x1u << 8) // (TC) Edge: rising edge

#define AT91C_TC_EEVTEDG_FALLING (0x2u << 8) // (TC) Edge: falling edge

#define AT91C_TC_EEVTEDG_BOTH (0x3u << 8) // (TC) Edge: each edge

#define AT91C_TC_EEVT (0x3u << 10) // (TC) External Event Selection

#define AT91C_TC_EEVT_NONE (0x0u << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input

#define AT91C_TC_EEVT_RISING (0x1u << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output

#define AT91C_TC_EEVT_FALLING (0x2u << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output

#define AT91C_TC_EEVT_BOTH (0x3u << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output

#define AT91C_TC_ENETRG (0x1u << 12) // (TC) External Event Trigger enable

#define AT91C_TC_WAVESEL (0x3u << 13) // (TC) Waveform Selection

#define AT91C_TC_WAVESEL_UP (0x0u << 13) // (TC) UP mode without atomatic trigger on RC Compare

#define AT91C_TC_WAVESEL_UP_AUTO (0x1u << 13) // (TC) UP mode with automatic trigger on RC Compare

#define AT91C_TC_WAVESEL_UPDOWN (0x2u << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare

#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3u << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare

#define AT91C_TC_CPCTRG (0x1u << 14) // (TC) RC Compare Trigger Enable

#define AT91C_TC_WAVE (0x1u << 15) // (TC)

#define AT91C_TC_ACPA (0x3u << 16) // (TC) RA Compare Effect on TIOA

#define AT91C_TC_ACPA_NONE (0x0u << 16) // (TC) Effect: none

#define AT91C_TC_ACPA_SET (0x1u << 16) // (TC) Effect: set

#define AT91C_TC_ACPA_CLEAR (0x2u << 16) // (TC) Effect: clear

#define AT91C_TC_ACPA_TOGGLE (0x3u << 16) // (TC) Effect: toggle

#define AT91C_TC_ACPC (0x3u << 18) // (TC) RC Compare Effect on TIOA

#define AT91C_TC_ACPC_NONE (0x0u << 18) // (TC) Effect: none

#define AT91C_TC_ACPC_SET (0x1u << 18) // (TC) Effect: set

#define AT91C_TC_ACPC_CLEAR (0x2u << 18) // (TC) Effect: clear

#define AT91C_TC_ACPC_TOGGLE (0x3u << 18) // (TC) Effect: toggle

#define AT91C_TC_AEEVT (0x3u << 20) // (TC) External Event Effect on TIOA

#define AT91C_TC_AEEVT_NONE (0x0u << 20) // (TC) Effect: none

#define AT91C_TC_AEEVT_SET (0x1u << 20) // (TC) Effect: set

#define AT91C_TC_AEEVT_CLEAR (0x2u << 20) // (TC) Effect: clear

#define AT91C_TC_AEEVT_TOGGLE (0x3u << 20) // (TC) Effect: toggle

#define AT91C_TC_ASWTRG (0x3u << 22) // (TC) Software Trigger Effect on TIOA

#define AT91C_TC_ASWTRG_NONE (0x0u << 22) // (TC) Effect: none

#define AT91C_TC_ASWTRG_SET (0x1u << 22) // (TC) Effect: set

#define AT91C_TC_ASWTRG_CLEAR (0x2u << 22) // (TC) Effect: clear

#define AT91C_TC_ASWTRG_TOGGLE (0x3u << 22) // (TC) Effect: toggle

#define AT91C_TC_BCPB (0x3u << 24) // (TC) RB Compare Effect on TIOB

#define AT91C_TC_BCPB_NONE (0x0u << 24) // (TC) Effect: none

#define AT91C_TC_BCPB_SET (0x1u << 24) // (TC) Effect: set

#define AT91C_TC_BCPB_CLEAR (0x2u << 24) // (TC) Effect: clear

#define AT91C_TC_BCPB_TOGGLE (0x3u << 24) // (TC) Effect: toggle

#define AT91C_TC_BCPC (0x3u << 26) // (TC) RC Compare Effect on TIOB

#define AT91C_TC_BCPC_NONE (0x0u << 26) // (TC) Effect: none

#define AT91C_TC_BCPC_SET (0x1u << 26) // (TC) Effect: set

#define AT91C_TC_BCPC_CLEAR (0x2u << 26) // (TC) Effect: clear

#define AT91C_TC_BCPC_TOGGLE (0x3u << 26) // (TC) Effect: toggle

#define AT91C_TC_BEEVT (0x3u << 28) // (TC) External Event Effect on TIOB

#define AT91C_TC_BEEVT_NONE (0x0u << 28) // (TC) Effect: none

#define AT91C_TC_BEEVT_SET (0x1u << 28) // (TC) Effect: set

#define AT91C_TC_BEEVT_CLEAR (0x2u << 28) // (TC) Effect: clear

#define AT91C_TC_BEEVT_TOGGLE (0x3u << 28) // (TC) Effect: toggle

#define AT91C_TC_BSWTRG (0x3u << 30) // (TC) Software Trigger Effect on TIOB

#define AT91C_TC_BSWTRG_NONE (0x0u << 30) // (TC) Effect: none

#define AT91C_TC_BSWTRG_SET (0x1u << 30) // (TC) Effect: set

#define AT91C_TC_BSWTRG_CLEAR (0x2u << 30) // (TC) Effect: clear

#define AT91C_TC_BSWTRG_TOGGLE (0x3u << 30) // (TC) Effect: toggle

#define AT91C_TC_COVFS (0x1u << 0) // (TC) Counter Overflow

#define AT91C_TC_LOVRS (0x1u << 1) // (TC) Load Overrun

#define AT91C_TC_CPAS (0x1u << 2) // (TC) RA Compare

#define AT91C_TC_CPBS (0x1u << 3) // (TC) RB Compare

#define AT91C_TC_CPCS (0x1u << 4) // (TC) RC Compare

#define AT91C_TC_LDRAS (0x1u << 5) // (TC) RA Loading

#define AT91C_TC_LDRBS (0x1u << 6) // (TC) RB Loading

#define AT91C_TC_ETRCS (0x1u << 7) // (TC) External Trigger

#define AT91C_TC_ETRGS (0x1u << 16) // (TC) Clock Enabling

#define AT91C_TC_MTIOA (0x1u << 17) // (TC) TIOA Mirror

#define AT91C_TC_MTIOB (0x1u << 18) // (TC) TIOA Mirror

typedef struct _AT91S_TCB {

AT91S_TC TCB_TC0; // TC Channel 0

AT91_REG Reserved0[4]; //

AT91S_TC TCB_TC1; // TC Channel 1

AT91_REG Reserved1[4]; //

AT91S_TC TCB_TC2; // TC Channel 2

AT91_REG Reserved2[4]; //

AT91_REG TCB_BCR; // TC Block Control Register

AT91_REG TCB_BMR; // TC Block Mode Register

} AT91S_TCB, *AT91PS_TCB;

#define AT91C_TCB_SYNC (0x1u << 0) // (TCB) Synchro Command

#define AT91C_TCB_TC0XC0S (0x1u << 0) // (TCB) External Clock Signal 0 Selection

#define AT91C_TCB_TC0XC0S_TCLK0 0x0u // (TCB) TCLK0 connected to XC0

#define AT91C_TCB_TC0XC0S_NONE 0x1u // (TCB) None signal connected to XC0

#define AT91C_TCB_TC0XC0S_TIOA1 0x2u // (TCB) TIOA1 connected to XC0

#define AT91C_TCB_TC0XC0S_TIOA2 0x3u // (TCB) TIOA2 connected to XC0

#define AT91C_TCB_TC1XC1S (0x1u << 2) // (TCB) External Clock Signal 1 Selection

#define AT91C_TCB_TC1XC1S_TCLK1 (0x0u << 2) // (TCB) TCLK1 connected to XC1

#define AT91C_TCB_TC1XC1S_NONE (0x1u << 2) // (TCB) None signal connected to XC1

#define AT91C_TCB_TC1XC1S_TIOA0 (0x2u << 2) // (TCB) TIOA0 connected to XC1

#define AT91C_TCB_TC1XC1S_TIOA2 (0x3u << 2) // (TCB) TIOA2 connected to XC1

#define AT91C_TCB_TC2XC2S (0x1u << 4) // (TCB) External Clock Signal 2 Selection

#define AT91C_TCB_TC2XC2S_TCLK2 (0x0u << 4) // (TCB) TCLK2 connected to XC2

#define AT91C_TCB_TC2XC2S_NONE (0x1u << 4) // (TCB) None signal connected to XC2

#define AT91C_TCB_TC2XC2S_TIOA0 (0x2u << 4) // (TCB) TIOA0 connected to XC2

#define AT91C_TCB_TC2XC2S_TIOA2 (0x3u << 4) // (TCB) TIOA2 connected to XC2

typedef struct _AT91S_UHP {

AT91_REG UHP_HcRevision; // Revision

AT91_REG UHP_HcControl; // Operating modes for the Host Controller

AT91_REG UHP_HcCommandStatus; // Command & status Register

AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register

AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register

AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register

AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area

AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor

AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list

AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register

AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list

AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list

AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor

AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs

AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame

AT91_REG UHP_HcFmNumber; // Frame number

AT91_REG UHP_HcPeriodicStart; // Periodic Start

AT91_REG UHP_HcLSThreshold; // LS Threshold

AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A

AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B

AT91_REG UHP_HcRhStatus; // Root Hub Status register

AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register

} AT91S_UHP, *AT91PS_UHP;

typedef struct _AT91S_EMAC {

AT91_REG EMAC_CTL; // Network Control Register

AT91_REG EMAC_CFG; // Network Configuration Register

AT91_REG EMAC_SR; // Network Status Register

AT91_REG EMAC_TAR; // Transmit Address Register

AT91_REG EMAC_TCR; // Transmit Control Register

AT91_REG EMAC_TSR; // Transmit Status Register

AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer

AT91_REG Reserved0[1]; //

AT91_REG EMAC_RSR; // Receive Status Register

AT91_REG EMAC_ISR; // Interrupt Status Register

AT91_REG EMAC_IER; // Interrupt Enable Register

AT91_REG EMAC_IDR; // Interrupt Disable Register

AT91_REG EMAC_IMR; // Interrupt Mask Register

AT91_REG EMAC_MAN; // PHY Maintenance Register

AT91_REG Reserved1[2]; //

AT91_REG EMAC_FRA; // Frames Transmitted OK Register

AT91_REG EMAC_SCOL; // Single Collision Frame Register

AT91_REG EMAC_MCOL; // Multiple Collision Frame Register

AT91_REG EMAC_OK; // Frames Received OK Register

AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register

AT91_REG EMAC_ALE; // Alignment Error Register

AT91_REG EMAC_DTE; // Deferred Transmission Frame Register

AT91_REG EMAC_LCOL; // Late Collision Register

AT91_REG EMAC_ECOL; // Excessive Collision Register

AT91_REG EMAC_CSE; // Carrier Sense Error Register

AT91_REG EMAC_TUE; // Transmit Underrun Error Register

AT91_REG EMAC_CDE; // Code Error Register

AT91_REG EMAC_ELR; // Excessive Length Error Register

AT91_REG EMAC_RJB; // Receive Jabber Register

AT91_REG EMAC_USF; // Undersize Frame Register

AT91_REG EMAC_SQEE; // SQE Test Error Register

AT91_REG EMAC_DRFC; // Discarded RX Frame Register

AT91_REG Reserved2[3]; //

AT91_REG EMAC_HSH; // Hash Address High[63:32]

AT91_REG EMAC_HSL; // Hash Address Low[31:0]

AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes

AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes

AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes

AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes

AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes

AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes

AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes

AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr

} AT91S_EMAC, *AT91PS_EMAC;

#define AT91C_EMAC_LB (0x1u << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.

#define AT91C_EMAC_LBL (0x1u << 1) // (EMAC) Loopback local.

#define AT91C_EMAC_RE (0x1u << 2) // (EMAC) Receive enable.

#define AT91C_EMAC_TE (0x1u << 3) // (EMAC) Transmit enable.

#define AT91C_EMAC_MPE (0x1u << 4) // (EMAC) Management port enable.

#define AT91C_EMAC_CSR (0x1u << 5) // (EMAC) Clear statistics registers.

#define AT91C_EMAC_ISR (0x1u << 6) // (EMAC) Increment statistics registers.

#define AT91C_EMAC_WES (0x1u << 7) // (EMAC) Write enable for statistics registers.

#define AT91C_EMAC_BP (0x1u << 8) // (EMAC) Back pressure.

#define AT91C_EMAC_SPD (0x1u << 0) // (EMAC) Speed.

#define AT91C_EMAC_FD (0x1u << 1) // (EMAC) Full duplex.

#define AT91C_EMAC_BR (0x1u << 2) // (EMAC) Bit rate.

#define AT91C_EMAC_CAF (0x1u << 4) // (EMAC) Copy all frames.

#define AT91C_EMAC_NBC (0x1u << 5) // (EMAC) No broadcast.

#define AT91C_EMAC_MTI (0x1u << 6) // (EMAC) Multicast hash enable

#define AT91C_EMAC_UNI (0x1u << 7) // (EMAC) Unicast hash enable.

#define AT91C_EMAC_BIG (0x1u << 8) // (EMAC) Receive 1522 bytes.

#define AT91C_EMAC_EAE (0x1u << 9) // (EMAC) External address match enable.

#define AT91C_EMAC_CLK (0x3u << 10) // (EMAC)

#define AT91C_EMAC_CLK_HCLK_8 (0x0u << 10) // (EMAC) HCLK divided by 8

#define AT91C_EMAC_CLK_HCLK_16 (0x1u << 10) // (EMAC) HCLK divided by 16

#define AT91C_EMAC_CLK_HCLK_32 (0x2u << 10) // (EMAC) HCLK divided by 32

#define AT91C_EMAC_CLK_HCLK_64 (0x3u << 10) // (EMAC) HCLK divided by 64

#define AT91C_EMAC_RTY (0x1u << 12) // (EMAC)

#define AT91C_EMAC_RMII (0x1u << 13) // (EMAC)

#define AT91C_EMAC_MDIO (0x1u << 1) // (EMAC)

#define AT91C_EMAC_IDLE (0x1u << 2) // (EMAC)

#define AT91C_EMAC_LEN (0x7FFu << 0) // (EMAC)

#define AT91C_EMAC_NCRC (0x1u << 15) // (EMAC)

#define AT91C_EMAC_OVR (0x1u << 0) // (EMAC)

#define AT91C_EMAC_COL (0x1u << 1) // (EMAC)

#define AT91C_EMAC_RLE (0x1u << 2) // (EMAC)

#define AT91C_EMAC_TXIDLE (0x1u << 3) // (EMAC)

#define AT91C_EMAC_BNQ (0x1u << 4) // (EMAC)

#define AT91C_EMAC_COMP (0x1u << 5) // (EMAC)

#define AT91C_EMAC_UND (0x1u << 6) // (EMAC)

#define AT91C_EMAC_BNA (0x1u << 0) // (EMAC)

#define AT91C_EMAC_REC (0x1u << 1) // (EMAC)

#define AT91C_EMAC_DONE (0x1u << 0) // (EMAC)

#define AT91C_EMAC_RCOM (0x1u << 1) // (EMAC)

#define AT91C_EMAC_RBNA (0x1u << 2) // (EMAC)

#define AT91C_EMAC_TOVR (0x1u << 3) // (EMAC)

#define AT91C_EMAC_TUND (0x1u << 4) // (EMAC)

#define AT91C_EMAC_RTRY (0x1u << 5) // (EMAC)

#define AT91C_EMAC_TBRE (0x1u << 6) // (EMAC)

#define AT91C_EMAC_TCOM (0x1u << 7) // (EMAC)

#define AT91C_EMAC_TIDLE (0x1u << 8) // (EMAC)

#define AT91C_EMAC_LINK (0x1u << 9) // (EMAC)

#define AT91C_EMAC_ROVR (0x1u << 10) // (EMAC)

#define AT91C_EMAC_HRESP (0x1u << 11) // (EMAC)

#define AT91C_EMAC_DATA (0xFFFFu << 0) // (EMAC)

#define AT91C_EMAC_CODE (0x3u << 16) // (EMAC)

#define AT91C_EMAC_REGA (0x1Fu << 18) // (EMAC)

#define AT91C_EMAC_PHYA (0x1Fu << 23) // (EMAC)

#define AT91C_EMAC_RW (0x3u << 28) // (EMAC)

#define AT91C_EMAC_HIGH (0x1u << 30) // (EMAC)

#define AT91C_EMAC_LOW (0x1u << 31) // (EMAC)

typedef struct _AT91S_EBI {

AT91_REG EBI_CSA; // Chip Select Assignment Register

AT91_REG EBI_CFGR; // Configuration Register

} AT91S_EBI, *AT91PS_EBI;

#define AT91C_EBI_CS0A (0x1u << 0) // (EBI) Chip Select 0 Assignment

#define AT91C_EBI_CS0A_SMC 0x0u // (EBI) Chip Select 0 is assigned to the Static Memory Controller.

#define AT91C_EBI_CS0A_BFC 0x1u // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.

#define AT91C_EBI_CS1A (0x1u << 1) // (EBI) Chip Select 1 Assignment

#define AT91C_EBI_CS1A_SMC (0x0u << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.

#define AT91C_EBI_CS1A_SDRAMC (0x1u << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.

#define AT91C_EBI_CS3A (0x1u << 3) // (EBI) Chip Select 3 Assignment

#define AT91C_EBI_CS3A_SMC (0x0u << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.

#define AT91C_EBI_CS3A_SMC_SmartMedia (0x1u << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.

#define AT91C_EBI_CS4A (0x1u << 4) // (EBI) Chip Select 4 Assignment

#define AT91C_EBI_CS4A_SMC (0x0u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.

#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.

#define AT91C_EBI_DBPUC (0x1u << 0) // (EBI) Data Bus Pull-Up Configuration

#define AT91C_EBI_EBSEN (0x1u << 1) // (EBI) Bus Sharing Enable

typedef struct _AT91S_SMC2 {

AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register

} AT91S_SMC2, *AT91PS_SMC2;

#define AT91C_SMC2_NWS (0x7Fu << 0) // (SMC2) Number of Wait States

#define AT91C_SMC2_WSEN (0x1u << 7) // (SMC2) Wait State Enable

#define AT91C_SMC2_TDF (0xFu << 8) // (SMC2) Data Float Time

#define AT91C_SMC2_BAT (0x1u << 12) // (SMC2) Byte Access Type

#define AT91C_SMC2_DBW (0x1u << 13) // (SMC2) Data Bus Width

#define AT91C_SMC2_DBW_16 (0x1u << 13) // (SMC2) 16-bit.

#define AT91C_SMC2_DBW_8 (0x2u << 13) // (SMC2) 8-bit.

#define AT91C_SMC2_DRP (0x1u << 15) // (SMC2) Data Read Protocol

#define AT91C_SMC2_ACSS (0x3u << 16) // (SMC2) Address to Chip Select Setup

#define AT91C_SMC2_ACSS_STANDARD (0x0u << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.

#define AT91C_SMC2_ACSS_1_CYCLE (0x1u << 16) // (SMC2) One cycle less at the beginning and the end of the access.

#define AT91C_SMC2_ACSS_2_CYCLES (0x2u << 16) // (SMC2) Two cycles less at the beginning and the end of the access.

#define AT91C_SMC2_ACSS_3_CYCLES (0x3u << 16) // (SMC2) Three cycles less at the beginning and the end of the access.

#define AT91C_SMC2_RWSETUP (0x7u << 24) // (SMC2) Read and Write Signal Setup Time

#define AT91C_SMC2_RWHOLD (0x7u << 29) // (SMC2) Read and Write Signal Hold Time

typedef struct _AT91S_SDRC {

AT91_REG SDRC_MR; // SDRAM Controller Mode Register

AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register

AT91_REG SDRC_CR; // SDRAM Controller Configuration Register

AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register

AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register

AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register

AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register

AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register

AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register

} AT91S_SDRC, *AT91PS_SDRC;

#define AT91C_SDRC_MODE (0xFu << 0) // (SDRC) Mode

#define AT91C_SDRC_MODE_NORMAL_CMD 0x0u // (SDRC) Normal Mode

#define AT91C_SDRC_MODE_NOP_CMD 0x1u // (SDRC) NOP Command

#define AT91C_SDRC_MODE_PRCGALL_CMD 0x2u // (SDRC) All Banks Precharge Command

#define AT91C_SDRC_MODE_LMR_CMD 0x3u // (SDRC) Load Mode Register Command

#define AT91C_SDRC_MODE_RFSH_CMD 0x4u // (SDRC) Refresh Command

#define AT91C_SDRC_DBW (0x1u << 4) // (SDRC) Data Bus Width

#define AT91C_SDRC_DBW_32_BITS (0x0u << 4) // (SDRC) 32 Bits datas bus

#define AT91C_SDRC_DBW_16_BITS (0x1u << 4) // (SDRC) 16 Bits datas bus

#define AT91C_SDRC_COUNT (0xFFFu << 0) // (SDRC) Refresh Counter

#define AT91C_SDRC_NC (0x3u << 0) // (SDRC) Number of Column Bits

#define AT91C_SDRC_NC_8 0x0u // (SDRC) 8 Bits

#define AT91C_SDRC_NC_9 0x1u // (SDRC) 9 Bits

#define AT91C_SDRC_NC_10 0x2u // (SDRC) 10 Bits

#define AT91C_SDRC_NC_11 0x3u // (SDRC) 11 Bits

#define AT91C_SDRC_NR (0x3u << 2) // (SDRC) Number of Row Bits

#define AT91C_SDRC_NR_11 (0x0u << 2) // (SDRC) 11 Bits

#define AT91C_SDRC_NR_12 (0x1u << 2) // (SDRC) 12 Bits

#define AT91C_SDRC_NR_13 (0x2u << 2) // (SDRC) 13 Bits

#define AT91C_SDRC_NB (0x1u << 4) // (SDRC) Number of Banks

#define AT91C_SDRC_NB_2_BANKS (0x0u << 4) // (SDRC) 2 banks

#define AT91C_SDRC_NB_4_BANKS (0x1u << 4) // (SDRC) 4 banks

#define AT91C_SDRC_CAS (0x3u << 5) // (SDRC) CAS Latency

#define AT91C_SDRC_CAS_2 (0x2u << 5) // (SDRC) 2 cycles

#define AT91C_SDRC_TWR (0xFu << 7) // (SDRC) Number of Write Recovery Time Cycles

#define AT91C_SDRC_TRC (0xFu << 11) // (SDRC) Number of RAS Cycle Time Cycles

#define AT91C_SDRC_TRP (0xFu << 15) // (SDRC) Number of RAS Precharge Time Cycles

#define AT91C_SDRC_TRCD (0xFu << 19) // (SDRC) Number of RAS to CAS Delay Cycles

#define AT91C_SDRC_TRAS (0xFu << 23) // (SDRC) Number of RAS Active Time Cycles

#define AT91C_SDRC_TXSR (0xFu << 27) // (SDRC) Number of Command Recovery Time Cycles

#define AT91C_SDRC_SRCB (0x1u << 0) // (SDRC) Self-refresh Command Bit

#define AT91C_SDRC_LPCB (0x1u << 0) // (SDRC) Low-power Command Bit

#define AT91C_SDRC_RES (0x1u << 0) // (SDRC) Refresh Error Status

typedef struct _AT91S_BFC {

AT91_REG BFC_MR; // BFC Mode Register

} AT91S_BFC, *AT91PS_BFC;

#define AT91C_BFC_BFCOM (0x3u << 0) // (BFC) Burst Flash Controller Operating Mode

#define AT91C_BFC_BFCOM_DISABLED 0x0u // (BFC) NPCS0 is driven by the SMC or remains high.

#define AT91C_BFC_BFCOM_ASYNC 0x1u // (BFC) Asynchronous

#define AT91C_BFC_BFCOM_BURST_READ 0x2u // (BFC) Burst Read

#define AT91C_BFC_BFCC (0x3u << 2) // (BFC) Burst Flash Controller Operating Mode

#define AT91C_BFC_BFCC_MCK (0x1u << 2) // (BFC) Master Clock.

#define AT91C_BFC_BFCC_MCK_DIV_2 (0x2u << 2) // (BFC) Master Clock divided by 2.

#define AT91C_BFC_BFCC_MCK_DIV_4 (0x3u << 2) // (BFC) Master Clock divided by 4.

#define AT91C_BFC_AVL (0xFu << 4) // (BFC) Address Valid Latency

#define AT91C_BFC_PAGES (0x7u << 8) // (BFC) Page Size

#define AT91C_BFC_PAGES_NO_PAGE (0x0u << 8) // (BFC) No page handling.

#define AT91C_BFC_PAGES_16 (0x1u << 8) // (BFC) 16 bytes page size.

#define AT91C_BFC_PAGES_32 (0x2u << 8) // (BFC) 32 bytes page size.

#define AT91C_BFC_PAGES_64 (0x3u << 8) // (BFC) 64 bytes page size.

#define AT91C_BFC_PAGES_128 (0x4u << 8) // (BFC) 128 bytes page size.

#define AT91C_BFC_PAGES_256 (0x5u << 8) // (BFC) 256 bytes page size.

#define AT91C_BFC_PAGES_512 (0x6u << 8) // (BFC) 512 bytes page size.

#define AT91C_BFC_PAGES_1024 (0x7u << 8) // (BFC) 1024 bytes page size.

#define AT91C_BFC_OEL (0x3u << 12) // (BFC) Output Enable Latency

#define AT91C_BFC_BAAEN (0x1u << 16) // (BFC) Burst Address Advance Enable

#define AT91C_BFC_BFOEH (0x1u << 17) // (BFC) Burst Flash Output Enable Handling

#define AT91C_BFC_MUXEN (0x1u << 18) // (BFC) Multiplexed Bus Enable

#define AT91C_BFC_RDYEN (0x1u << 19) // (BFC) Ready Enable Mode

#define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register

#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register

#define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals

#define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area

#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register

#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register

#define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register

#define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register

#define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register

#define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register

#define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register

#define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register

#define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register

#define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register

#define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register

#define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register

#define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register

#define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register

#define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register

#define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register

#define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register

#define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register

#define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register

#define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register

#define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register

#define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register

#define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register

#define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register

#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register

#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register

#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register

#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register

#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register

#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register

#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register

#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register

#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register

#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register

#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register

#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register

#define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register

#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register

#define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register

#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register

#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register

#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register

#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register

#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register

#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register

#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register

#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register

#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register

#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register

#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register

#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register

#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register

#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register